- 您现在的位置：买卖IC网 > PDF目录385870 > ST6391B1 (意法半导体) MOSFET; Transistor Polarity:Dual N Channel; Continuous Drain Current, Id:2.6A; On-Resistance, Rds(on):0.18ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No PDF资料下载
参数资料
| 型号： | ST6391B1 |
| 厂商： | 意法半导体 |
| 英文描述： | MOSFET; Transistor Polarity:Dual N Channel; Continuous Drain Current, Id:2.6A; On-Resistance, Rds(on):0.18ohm; Package/Case:8-SOIC; Leaded Process Compatible:No; Mounting Type:surface mount; Peak Reflow Compatible (260 C):No |
| 中文描述： | 8位微控制器HCMOS电视频率合成带OSD |
| 文件页数： | 21/68页 |
| 文件大小： | 560K |
| 代理商： | ST6391B1 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页当前第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
MEMORY SPACES
(Continued)
Additional Notes on Parallel Mode.
If the user
wants to perform a parallel programming the first
action should betheset toone thePE bit;from this
moment the first time the EEPROM will be ad-
dressed in writing, the ROW address will be
latched and it will be possible to change it only at
the end ofthe programming procedureor byreset-
ting PE without programming the EEPROM. After
the ROWaddress latching the Core can “see” just
one EEPROMrow (the selected one) and any at-
tempt to write or read other rows will produce er-
rors. Donot read the EEPROM while PEis set.
As soon asPEbitis set,the 8volatile ROWlatches
are cleared. From this moment the user can load
data in the whole ROWor just in a subset.PS set-
ting willmodifythe EEPROM registerscorrespond-
ing to the ROW latches accessed after PE. For
example, if the software sets PE and accesses
EEPROM in writing at addresses18h,1Ah,1Bhand
thensetsPS,thesethreeregisterswill bemodifiedat
thesame time;the remainingbyteswill haveno par-
ticular content.Note thatPE is internallyreset at the
endof theprogrammingprocedure.Thisimpliesthat
the user must set PE bit between two parallel pro-
grammingprocedures.Anywaytheusercansetand
thenresetPEwithoutperforminganyEEPROMpro-
gramming. PSis a setonly bitand is internallyreset
at the end of the programmingprocedure.Note that
if theusertries toset PSwhilePEis notsettherewill
not be any programming procedure and the PS bit
will be unaffected.ConsequentlyPS bit can not be
setif ENis low.PScan beaffectedbytheusersetif,
andonly if, ENandPEbitsarealso setto one.
INTERRUPT
The ST639x Core can manage 4 different mask-
able interruptsources, plus one non-maskable in-
terrupt source (top priority level interrupt). Each
source isassociated with aparticular interruptvec-
tor that contains a Jump instruction to the related
interrupt service routine. Each vector is located in
the Program Space at a particular address (see
Table 6). When a source provides an interruptre-
quest, and the request processingis alsoenabled
by theST639x Core, then the PC registerisloaded
with the address of the interrupt vector (i.e. of the
Jumpinstruction).Finally,thePCisloaded withthe
address of the Jump instruction and the interrupt
routine is processed.
The relationship between vector and source and
the associatedpriority is hardware fixed for the dif-
ferentST639xdevices.Forsomeinterrupt sources
it is also possible to select by softwarethe kind of
event that will generatethe interrupt.
All interruptscan bedisabled by writingto the GEN
bit (global interruptenable) of the interrupt option
register (address C8h). After a reset,ST639x is in
non maskable interrupt mode, so no interrupts will
be accepted and NMI flags will be used, until a
RETI instructionis executed.Ifan interruptis exe-
cuted, one special cycle is made by the core, dur-
ing that the PC is set to the related interruptvector
address. A jump instruction at this address has to
redirect programexecution to the beginningof the
relatedinterruptroutine.Theinterrupt detectingcy-
cle, also resets the related interrupt flag (not avail-
able to the user), so that another interrupt can be
stored for this current vector, while its driver is un-
der execution.
If additionalinterruptsarrive fromthesamesource,
they will be lost. NMI can interrupt other interrupt
routines at any time,while other interrupts cannot
interrupt each other. If more than one interrupt is
waiting forservice, they are executed according to
their priority. The lower the number, the higher the
priority. Priority is, therefore, fixed. Interrupts are
checked during the last cycle of an instruction
(RETI included). Level sensitive interrupts have to
be validduring this period.
ST6391,92,93,95,97,99
17/64
相关PDF资料 |
PDF描述 |
|---|---|
| ST6392 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6393 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6395 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6397 | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6399 | MOSFET; Transistor Polarity:P Channel; Drain Source Voltage, Vds:-30V; Continuous Drain Current, Id:-4.1A; On-Resistance, Rds(on):0.08ohm; Rds(on) Test Voltage, Vgs:-10V; Package/Case:8-1206; Leaded Process Compatible:No |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST6392 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6392B1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6393 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6393B1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6395 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
发布紧急采购，3分钟左右您将得到回复。