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参数资料
| 型号： | ST6393 |
| 厂商： | 意法半导体 |
| 英文描述： | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| 中文描述： | 8位微控制器HCMOS电视频率合成带OSD |
| 文件页数： | 39/68页 |
| 文件大小： | 560K |
| 代理商： | ST6393 |
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Start/StopAcknowledge.
Thetiming specsofthe
S-BUS protocol require that data on the SDA (only
on this line for I
2
CBUS) and SEN lines be stable
during the “high” time of SCL. Two exceptions to
this rule are foreseen and they are used to signal
the startand stopcondition of datatransfer.
-
On S-BUS by a transition of the SEN line (10
Start, 01 Stop) while the SCL line is at high
level.
-
On I
2
CBUS by a transition of the SDA line (10
Start, 01 Stop) while the SCL line is at high
level.
Data are transmitted in 8-bit groups; after each
group, aninth bit is interposed,with thepurpose of
acknowledging the transmitting sequence (the
transmitdeviceplacea “1” onthe bus,the acknow-
ledgingreceiver a “0”).
Interface Protocol.
This paragraphdeals with the
description of data protocol structure. The inter-
face protocolincludes:
- A startcondition
- A “slave chip address” byte, transmitted by the
master,containingtwo differentinformation:
a.
the code identifying the device the master
wants to address(this informationis presentin
the first sevenbits)
b.
the direction of transmission on the bus (this
information is given in the 8th bit of the byte);
“0” means “Write”, that is from the master to
the slave, while “1” means “Read”. The ad-
dressed slave mustalways acknowledge.
SERIAL PERIPHERAL INTERFACE
(Continued)
The sequence from, nowon, is different according
to the value ofR/W bit.
1. R/W = “0” (Write)
In all the following bytes the master acts as trans-
mitter; the sequencefollows with:
a.
anoptionaldata byteto address(if needed)the
slave locationto be written (it canbe a wordad-
dressin a memory or a registeraddress,etc.).
b.
a “data” byte which will be written at the ad-
dressgiven in theprevious byte.
c.
furtherdata bytes.
d.
a STOPcondition
A data transferis always terminated bya stop con-
dition generatedfrom the master. The ST639x pe-
ripheral must finish with a stop condition before
another startisgiven. Figure 44 showsanexample
of write operation.
2. R/W = “1” (Read)
In this case the slave acts as transmitter and,
therefore, the transmissiondirection ischanged. In
read mode two differentconditions can be consid-
ered:
a.
The master reads slaveimmediately after first
byte. In this case after the slaveaddress sent
from the master with read condition enabled
the master transmitter becomes master re-
ceiver and the slave receiver becomes slave
transmitter.
b.
The master reads a specified registeror loca-
tion of the slave.In thiscase the first sent byte
will containthe slaveaddress with write condi-
tion enabled, then the second byte will specify
the address of the register to be read. At this
moment a new startis given together with the
slave addressin read modeand theprocedure
will proceedas described in previous point “a”.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST6393B1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6395 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6395B1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6397 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6397B1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
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