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| 型号： | ST70136B |
| 厂商： | 意法半导体 |
| 英文描述： | CPE ADSL ANALOG FRONT END |
| 中文描述： | 终端ADSL模拟前端 |
| 文件页数： | 8/24页 |
| 文件大小： | 361K |
| 代理商： | ST70136B |
ST70136
8/24
4 - FUNCTIONAL DESCRIPTION
4.1 - General
The ST70136 consists of the following functional
blocks:
– Transmit Signal Path
– Receive Signal Path
– Bias Voltage and Current Generation
– Digital Data Interface
– Control Serial Interface
– Tone Detector
– Power Down mode management
4.2 - Transmit Path Description
The transmit path contains the 14-bit digital to
analog converter (DAC) necessary to generate
the transmit signal from a 16-bit digital input word.
This transmit signal is then scaled by the on chip
programmable gain amplifier (TxPGA) from 0 to
-15dB in 1dB steps. The scaled output signal is
then driven off chip to the external filters and
power amplifier (PA) which drives the DMT signal
to the subscriber loop. The transmit path is fully
differential.
4.3 - Receive Path Description
The receive path contains first an attenuator
(which allows the selection between 4 attenuated
versions of the signal) followed by a programma-
ble gain amplifier (RxPGA), a 1st order low pass
anti-aliasing filter, and a 12-bit analog to digital
converter (ADC). The RxPGA gain is digitally pro-
grammable from 0 to 31dB in 1dB steps. The
receive path is fully differential.
4.4 - VCXO
The ST70136 contains the circuits required to
construct an internal VCXO. It is divided in a crys-
tal driver and an auxiliary 8 bits DAC for timing
recovery. The crystal driver is able to operate at
35.328MHz.
The DAC which is driven by the CTRLIN pin (the
input of the Serial Control Interface), provides a
current output with 8 bits resolution and can be
used to tune the crystal frequency with the help of
external components. A time constant between
DAC input and VCXOUT can be introduced (via
CTRLIN interface) and programmed with the help
of an external capacitor (on VCOCAP pin).
4.5 - Bias Voltage and Current Generation
The bias circuitry contains a bandgap voltage ref-
erence from which the converters references and
analog ground voltages are generated. This block
also generates an accurate bias current using an
external resistor.
4.6 - Digital Data Interface
To facilitate data transfer between the ST70136
and the digital data pump, a 4-bit wide serial inter-
face for the transmit and receive path is incorpo-
rated into the AFE.
This interface consists of four transmit pins
(TX[0:3]), four receive pins (RX[0:3]), and the nec-
essary control signals (CLKM, CLKWD) to trans-
mit and receive the required data.
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PDF描述 |
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| ST70136G | CPE ADSL ANALOG FRONT END |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST70136G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:CPE ADSL ANALOG FRONT END |
| ST70136Q | 功能描述:射频无线杂项 ADSL Analg Front-End RoHS:否 制造商:Texas Instruments 工作频率:112 kHz to 205 kHz 电源电压-最大:3.6 V 电源电压-最小:3 V 电源电流:8 mA 最大功率耗散: 工作温度范围:- 40 C to + 110 C 封装 / 箱体:VQFN-48 封装:Reel |
| ST70137 | 制造商:STMicroelectronics 功能描述: |
| ST70137TQFP | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:UNICORNTM PCI & USB CONTROLLERLESS ADSL DMT TRANSCEIVER |
| ST70138 | 制造商:STMicroelectronics 功能描述: |
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