参数资料
型号: ST72101G2M6/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO28
封装: 0.300 INCH, PLASTIC, SOP-28
文件页数: 15/85页
文件大小: 879K
代理商: ST72101G2M6/XXX
Obsolete
Product(s)
- Obsolete
Product(s)
22/85
ST72101/ST72212/ST72213
POWER SAVING MODES (Cont’d)
4.4.4 Halt Mode
The Halt mode is the MCU lowest power con-
sumption mode. The Halt mode is entered by exe-
cuting the HALT instruction. The internal oscillator
is then turned off, causing all internal processing to
be stopped, including the operation of the on-chip
peripherals. The Halt mode cannot be used when
the watchdog is enabled, if the HALT instruction is
executed while the watchdog system is enabled, a
watchdog reset is generated thus resetting the en-
tire MCU.
When entering Halt mode, the I bit in the CC Reg-
ister is cleared so as to enable External Interrupts.
If an interrupt occurs, the CPU becomes active.
The MCU can exit the Halt mode upon reception of
an interrupt or a reset. Refer to the Interrupt Map-
ping Table. The oscillator is then turned on and a
stabilization time is provided before releasing CPU
operation. The stabilization time is 4096 CPU clock
cycles.
After the start up delay, the CPU continues oper-
ation by servicing the interrupt which wakes it up or
by fetching the reset vector if a reset wakes it up.
Figure 18. HALT Flow Chart
N
EXTERNAL
INTERRUPT1)
RESET
HALT INSTRUCTION
4096 CPU CLOCK
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CYCLES DELAY
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK2)
I-BIT
ON
OFF
SET
ON
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
OFF
CLEARED
OFF
Y
WDG
ENABLED?
N
Y
RESET
WATCHDOG
1) or some specific interrupts
Note: Before servicing an interrupt, the CC register is
pushed on the stack. The I-Bit is set during the inter-
rupt routine and cleared when the CC register is
popped.
CPU CLOCK
OSCILLATOR
PERIPH. CLOCK
I-BIT
ON
SET
ON
2) if reset PERIPH. CLOCK = ON ; if interrupt
PERIPH. CLOCK = OFF
22
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