参数资料
型号: ST72213G1M6/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO28
封装: 0.300 INCH, PLASTIC, SOP-28
文件页数: 9/85页
文件大小: 879K
代理商: ST72213G1M6/XXX
Obsolete
Product(s)
- Obsolete
Product(s)
17/85
ST72101/ST72212/ST72213
3.2 RESET
3.2.1 Introduction
There are three sources of Reset:
– RESET pin (external source)
– Power-On Reset (Internal source)
– WATCHDOG (Internal Source)
The Reset Service Routine vector is located at ad-
dress FFFEh-FFFFh.
3.2.2 External Reset
The RESET pin is both an input and an open-drain
output with integrated pull-up resistor. When one
of the internal Reset sources is active, the Reset
pin is driven low , for a duration of tRESET, to reset
the whole application.
3.2.3 Reset Operation
The duration of the Reset state is a minimum of
4096 internal CPU Clock cycles. During the Reset
state, all I/Os take their reset value.
A Reset signal originating from an external source
must have a duration of at least tPULSE in order to
be recognised. This detection is asynchronous
and therefore the MCU can enter Reset state even
in Halt mode.
At the end of the Reset cycle, the MCU may be
held in the Reset state by an External Reset sig-
nal. The RESET pin may thus be used to ensure
VDD has risen to a point where the MCU can oper-
ate correctly before the user program is run. Fol-
lowing a Reset event, or after exiting Halt mode, a
4096 CPU Clock cycle delay period is initiated in
order to allow the oscillator to stabilise and to en-
sure that recovery has taken place from the Reset
state.
In the high state, the RESET pin is connected in-
ternally to a pull-up resistor (RON). This resistor
can be pulled low by external circuitry to reset the
device.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to use the exter-
nal connections shown in Figure 8.
3.2.4 Power-on Reset
This circuit detects the ramping up of VDD, and
generates a pulse that is used to reset the applica-
tion (at approximately VDD= 2V).
Power-On Reset is designed exclusively to cope
with power-up conditions, and should not be used
in order to attempt to detect a drop in the power
supply voltage.
Caution:
to re-initialize the Power-On Reset, the
power supply must fall below approximately 0.8V
(Vtn), prior to rising above 2V. If this condition is
not respected, on subsequent power-up the Reset
pulse may not be generated. An external Reset
pulse may be required to correctly reactivate the
circuit.
Figure 15. Reset Block Diagram
INTERNAL
RESET
WATCHDOG RESET
OSCILLATOR
SIGNAL
COU
NTE
R
RESET
TO ST7
RESET
POWER-ON RESET
VDD
RON
17
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