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| 型号： | ST72323K1T5/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32 |
| 封装： | 7 X 7 MM, PLASTIC, LQFP-32 |
| 文件页数： | 9/140页 |
| 文件大小： | 1386K |
| 代理商： | ST72323K1T5/XXX |
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11.8 I/O PORT PIN CHARACTERISTICS
11.8.1 General Characteristics
Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
3. When the current limitation is not possible, the VIN maximum must be respected, otherwise refer to IINJ(PIN) specifica-
tion. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. Refer to Section 11.2.2
on page 92 for more details.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example and leaving the I/O unconnected on the board or an external pull-up or pull-down resistor (see Figure 64). Data
based on design simulation and/or technology characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
scribed in Figure 65).
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 64. Unused I/O Pins configured as input
Figure 65. Typical IPU vs. VDD with VIN=VSS
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage (standard voltage
devices)1)
0.3xVDD
V
VIH
Input high level voltage 1)
0.7xVDD
V
Vhys
Schmitt trigger voltage hysteresis 2)
0.7
IINJ(PIN)
3)
Injected Current on other I/O pins
VDD=5V
±4
mA
ΣIINJ(PIN)3)
Total injected current (sum of all I/O and
control pins)
±25
Ilkg
Input leakage current
VSS ≤ VIN ≤ VDD
±1
A
IS
Static current consumption induced by each
floating input pin
Floating input mode4)
200
RPU
Weak pull-up equivalent resistor 5)
VIN=VSS
VDD=5V
50
120
250
k
CIO
I/O pin capacitance
5
pF
tf(IO)out
Output high to low level fall time 1)
CL=50pF
Between 10% and
90%
25
ns
tr(IO)out
Output low to high level rise time 1)
25
tw(IT)in
External interrupt pulse time 6)
1tCPU
10k
UNUSED I/O PORT
ST7XXX
10k
UNUSED I/O PORT
ST7XXX
VDD
Note: I/O can be left unconnected if it is configured as output
greater EMC robustness and lower cost.
(0 or 1) by the software. This has the advantage of
0
10
20
30
40
50
60
70
80
90
22.5
33.5
4
4.5
55.5
6
Vdd(V)
Ipu(
u
A
)
Ta=140°C
Ta=95°C
Ta=25°C
Ta=-45°C
1
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