参数资料
型号: ST72324K2T6/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP32
封装: TQFP-32
文件页数: 56/161页
文件大小: 2070K
代理商: ST72324K2T6/XXX
ST72324
149/161
14 ST72324 DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM/FASTROM).
ST72324 devices are ROM versions. ST72P324
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: they are factory-pro-
grammed HDFlash devices. FLASH devices are
shipped to customers with a default content (FFh),
while ROM/FASTROM factory coded parts contain
the code supplied by the customer. This implies
that FLASH devices have to be configured by the
customer using the Option Bytes while the ROM/
FASTROM devices are factory-configured.
14.1 FLASH OPTION BYTES
The option bytes allows the hardware configura-
tion of the microcontroller to be selected. They
have no address in the memory map and can be
accessed only in programming mode (for example
using a standard ST7 programming tool). The de-
fault content of the FLASH is fixed to FFh. To pro-
gram directly the FLASH devices using ICP,
FLASH devices are shipped to customers with the
internal RC clock source. In masked ROM devic-
es, the option bytes are fixed in hardware by the
ROM code (see option list).
OPTION BYTE 0
OPT7= WDG HALT
Watchdog and HALT mode
This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6= WDG SW
Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = CSS
Clock security system on/off
This option bit enables or disables the clock secu-
rity system function (CSS) which includes the
clock filter and the backup safe oscillator.
0: CSS enabled
1: CSS disabled
Caution: The CSS function is not guaranteed. Re-
OPT4:3= VD[1:0]
Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD) with a selected threshold for
the LVD and AVD (EVD+AVD).
Caution: If the medium or low thresholds are se-
lected, the detection may occur outside the speci-
fied operating voltage range. Below 3.8V, device
operation is not guaranteed. For details on the
AVD and LVD threshold levels refer to Section
OPT2:1 = Reserved, must be kept at default value.
OPT0= FMP_R
Flash memory read-out protection
This option indicates if the user flash memory is
protected against read-out piracy. This protection
is based on read and a write protection of the
memory in test modes and ICP mode. Erasing the
option bytes when the FMP_R option is selected
causes the whole user memory to be erased first,
and the device can be reprogrammed. Refer to
Section 4.3.1 and the ST7 Flash Programming
Reference Manual for more details.
0: Read-out protection enabled
1: Read-out protection disabled
STATIC OPTION BYTE 0
70
STATIC OPTION BYTE 1
70
WDG
CS
S
VD
Rese
rved
Rese
rved
FMP
_R
PK
G1
RS
TC
OSCTYPE
OSCRANGE
PLLO
FF
H
ALT
SW
10
1
0
2
10
Default
11100
1
0
1
Selected Low Voltage Detector
VD1
VD0
LVD and AVD Off
1
Lowest Threshold: (VDD~3V)
1
0
Med. Threshold (VDD~3.5V)
0
1
Highest Threshold (VDD~4V)
0
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