参数资料
型号: ST72325J4B6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: MICROCONTROLLER, PDIP42
封装: 0.600 INCH, ROHS COMPLIANT, PLASTIC, DIP-42
文件页数: 106/197页
文件大小: 3582K
代理商: ST72325J4B6
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ST72325xx
194/197
KNOWN LIMITATIONS (Cont’d)
15.1.4 SCI Wrong Break duration
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy
of
19200
baud
(fCPU=8MHz and SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
15.1.5 16-bit Timer PWM Mode
In PWM mode, the first PWM pulse is missed after
writing the value FFFCh in the OC1R register
(OC1HR, OC1LR). It leads to either full or no PWM
during a period, depending on the OLVL1 and
OLVL2 settings.
15.1.6
TIMD
set
simultaneously
with
OC
interrupt
If the 16-bit timer is disabled at the same time the
output compare event occurs then output compare
flag gets locked and cannot be cleared before the
timer is enabled again.
Impact on the application
If output compare interrupt is enabled, then the
output compare flag cannot be cleared in the timer
interrupt routine. Consequently the interrupt serv-
ice routine is called repeatedly.
Workaround
Disable the timer interrupt before disabling the tim-
er. Again while enabling, first enable the timer then
the timer interrupts.
Perform the following to disable the timer:
TACR1 or TBCR1 = 0x00h; // Disable the com-
pare interrupt
TACSR | or TBCSR | = 0x40; // Disable the timer
Perform the following to enable the timer again:
TACSR & or TBCSR &= ~0x40; // Enable the tim-
er
TACR1 or TBCR1 = 0x40; // Enable the compare
interrupt
15.1.7 I2C Multimaster
In multimaster configurations, if the ST7 I2C re-
ceives a START condition from another I2C mas-
ter after the START bit is set in the I2CCR register
and before the START condition is generated by
the ST7 I2C, it may ignore the START condition
from the other I2C master. In this case, the ST7
master will receive a NACK from the other device.
On reception of the NACK, ST7 can send a re-start
and Slave address to re-initiate communication
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ST72325J4T3 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface
ST72325J4T6 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface
ST72325J6B3 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface
ST72325J6B6 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface
ST72325J6T3 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-bit MCU with 16 to 60K Flash/ROM, ADC, CSS, 5 timers, SPI, SCI, I2C interface