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参数资料
| 型号： | ST72611F1M1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 0.300 INCH, PLASTIC, SOP-20 |
| 文件页数： | 11/77页 |
| 文件大小： | 1178K |
| 代理商： | ST72611F1M1 |
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ST7261
19/77
INTERRUPTS (Cont’d)
6.3 INTERRUPTS AND LOW POWER MODES
All interrupts allow the processor to exit the WAIT
low power mode. On the contrary, only external
and other specified interrupts allow the processor
to exit from the HALT modes (see column “Exit
from HALT” in “Interrupt Mapping” table). When
several pending interrupts are present while exit-
ing HALT mode, the first one serviced can only be
an interrupt with exit from HALT mode capability
and it is selected through the same decision proc-
ess shown in Figure 17.
Note: If an interrupt, that is not able to Exit from
HALT mode, is pending with the highest priority
when exiting HALT mode, this interrupt is serviced
after the first one serviced.
6.4 CONCURRENT & NESTED MANAGEMENT
different interrupt management modes. The first is
called concurrent mode and does not allow an in-
terrupt to be interrupted, unlike the nested mode in
Figure 19. The interrupt hardware priority is given
in this order from the lowest to the highest: MAIN,
IT4, IT3, IT2, IT1, IT0, TLI. The software priority is
given for each interrupt.
Warning: A stack overflow may occur without no-
tifying the software of the failure.
Figure 18. Concurrent Interrupt Management
Figure 19. Nested Interrupt Management
MAIN
IT4
IT2
IT1
TLI
IT1
MAIN
IT0
I1
HA
RD
WA
RE
P
R
IO
RIT
Y
SOFTWARE
3
3/0
3
11
11 / 10
11
RIM
IT
2
IT
1
IT
4
TLI
IT
3
IT
0
IT3
I0
10
PRIORITY
LEVEL
US
ED
S
T
ACK
=
10
BYT
ES
MAIN
IT2
TLI
MAIN
IT0
IT2
IT1
IT4
TLI
IT3
IT
0
HA
RDWA
R
E
P
R
IO
RIT
Y
3
2
1
3
3/0
3
11
00
01
11
RIM
IT1
IT4
IT1
IT2
IT3
I1
I0
11 / 10
10
SOFTWARE
PRIORITY
LEVEL
USE
D
ST
ACK
=
20
B
Y
TE
S
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