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参数资料
| 型号： | ST72621K4B1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32 |
| 封装： | 0.400 INCH, LEAD FREE, SHRINK, PLASTIC, DIP-32 |
| 文件页数： | 42/139页 |
| 文件大小： | 1264K |
| 代理商： | ST72621K4B1 |
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Doc ID 6996 Rev 5
15.3 SCI WRONG BREAK DURATION
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
– 20 bits instead of 10 bits if M=0
– 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
This affects all silicon revisions.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy
of
19200
baud
(fCPU=8MHz and SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
– Disable interrupts
– Reset and Set TE (IDLE request)
– Set and Reset SBK (Break Request)
– Re-enable interrupts
15.4 UNEXPECTED RESET FETCH
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
This affects all silicon revisions.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
15.5 HALT MODE POWER CONSUMPTION
WITH ADC ON
If the A/D converter is being used when Halt mode
is entered, the power consumption in Halt Mode
may exceed the maximum specified in the
datasheet.
This affects all silicon revisions.
Workaround
Switch off the ADC by software (ADON=0) before
executing a HALT instruction.
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