参数资料
型号: ST72C314J4TA
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
封装: 10 X 10 MM, ROHS COMPLIANT, TQFP-44
文件页数: 128/150页
文件大小: 3530K
代理商: ST72C314J4TA
ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto
79/150
SERIAL PERIPHERAL INTERFACE (Cont’d)
13.4.4.4 Write Collision Error
A write collision occurs when the software tries to
write to the DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.
Write collisions can occur both in master and slave
mode.
Note: A “read collision” will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.
In Slave mode
When the CPHA bit is set:
The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.
The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.
When the CPHA bit is reset:
Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.
For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.
In Master mode
Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.
The SS pin signal must be always high on the
master device.
WCOL bit
The WCOL bit in the SR register is set if a write
collision occurs.
No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).
Clearing the WCOL bit is done through a software
sequence (see Figure 45).
Figure 45. Clearing the WCOL bit (Write Collision Flag) Software Sequence
Clearing sequence after SPIF = 1 (end of a data byte transfer)
1st Step
Read SR
Read DR
Write DR
2nd Step
SPIF =0
WCOL=0
SPIF =0
WCOL=0 if no transfer has started
WCOL=1 if a transfer has started
Clearing sequence before SPIF = 1 (during a data byte transfer)
1st Step
2nd Step
WCOL=0
before the 2nd step
Read SR
Read DR
Note: Writing to the DR register
instead of reading in it does not
reset the WCOL bit.
Read SR
OR
THEN
相关PDF资料
PDF描述
ST72C334N2TC 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
ST72334N2TC/XXX 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64
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