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参数资料
型号： ST72F321J7T1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44
封装： 10 X 10 MM, PLASTIC, TQFP-44
文件页数： 171/176页
文件大小： 1112K
代理商： ST72F321J7T1
ST72321J
94/176
SERIAL PERIPHERAL INTERFACE (Cont’d)
CONTROL/STATUS REGISTER (SPICSR)
Read/Write (some bits Read Only)
Reset Value: 0000 0000 (00h)
Bit 7 = SPIF
Serial Peripheral Data Transfer Flag
(Read only).
This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-
proved by a clearing sequence.
1: Data transfer between the device and an exter-
nal device has been completed.
Note: While the SPIF bit is set, all writes to the DR
register are inhibited.
Bit 6 = WCOL
Write Collision status (Read only).
This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 56).
0: No write collision occurred
1: A write collision has been detected
Bit 5 = OVR S
PI Overrun error (Read only).
This bit is set by hardware when the byte currently
being received in the shift register is ready to be
transferred into the SPIDR register while SPIF = 1
(See Section 10.5.4.8). An interrupt is generated if
SPIE = 1 in SPICR register. The OVR bit is cleared
by software reading the SPICSR register.
0: No overrun error
1: Overrun error detected
Bit 4 = MODF
Mode Fault flag (Read only).
This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 10.5.4.7
Master Mode Fault). An SPI interrupt can be gen-
erated if SPIE=1 in the SPICR register. This bit is
cleared by a software sequence (An access to the
SPICSR register while MODF=1 followed by a
write to the SPICR register).
0: No master mode fault detected
1: A fault in master mode has been detected
Bits 3 = Reserved, must be kept cleared.
Bit 2 = SOD
SPI Output Disable.
This bit is set and cleared by software. When set it
disables the alternate function of the SPI output
(MOSI in master mode / MISO in slave mode)
0: SPI output not disabled
1: SPI output disabled
Bit 1 = SSM
SS Mode Selection.
This bit is set and cleared by software. When set, it
disables the alternate function of the SPI Slave
Select pin and use the SSI bit value instead.
0: Hardware mode (SS pin is used for Master/
Slave Selection).
1: Software mode (SSI bit is used for Master/Slave
Selection). SS is free to be used as a standard
I/O pin
Note: Master mode selection also depends on the
value of the MSTR bit in the SPICR register
Bit 0 = SSI
SS Internal Mode.
This bit is set and cleared by software. It replaces
pin SS of the SPI when bit SSM is set to 1. SSI bit
is active low slave select signal when SSM is set to
1.
0 : Slave selected
1 : Slave not selected
DATA I/O REGISTER (SPIDR)
Read/Write
Reset Value: Undefined
The SPIDR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.
Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.
Warning: A write to the SPIDR register places
data directly into the shift register for transmission.
A read to the SPIDR register returns the value lo-
cated in the buffer and not the content of the shift
register (see Figure 53).
70
SPIF
WCOL
OVR
MODF
-
SOD
SSM
SSI
70
D7
D6
D5
D4
D3
D2
D1
D0
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