参数资料
型号: ST72F324LK6T6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32
封装: 7 X 7 MM, TQFP-32
文件页数: 80/154页
文件大小: 3519K
代理商: ST72F324LK6T6
ST72324Lxx
31/154
INTERRUPTS (Cont’d)
Table 9. Interrupt Mapping
Notes:
1. Valid for ROM devices. For Flash devices only a RESET or MCC/RTC interrupt can be used to wake-
up from Active Halt mode.
7.6 EXTERNAL INTERRUPTS
7.6.1 I/O Port Interrupt Sensitivity
The external interrupt sensitivity is controlled by
the IPA, IPB and ISxx bits of the EICR register
(Figure 18). This control allows to have up to 4 fully
independent external interrupt source sensitivities.
Each external interrupt source can be generated
on four (or five) different events on the pin:
Falling edge
Rising edge
Falling and rising edge
Falling edge and low level
Rising edge and high level (only for ei0 and ei2)
To guarantee correct functionality, the sensitivity
bits in the EICR register can be modified only
when the I1 and I0 bits of the CC register are both
set to 1 (level 3). This means that interrupts must
be disabled before changing sensitivity.
The pending interrupts are cleared when disabling
these interrupts by setting their I0_x and I1_x in
the matching ISPR
Source
Block
Description
Register
Label
Priority
Order
Exit
from
HALT
Exit
from
Active
HALT
Address
Vector
RESET
Reset
N/A
yes
FFFEh-FFFFh
TRAP
Software interrupt
no
FFFCh-FFFDh
0
Not used
FFFAh-FFFBh
1
MCC/RTC
Main clock controller time base inter-
rupt
MCCSR
Higher
Priority
no
yes
FFF8h-FFF9h
2
ei0
External interrupt port A3..0
N/A
yes
yes1)
FFF6h-FFF7h
3
ei1
External interrupt port F2..0
yes
yes1)
FFF4h-FFF5h
4
ei2
External interrupt port B3..0
yes
yes1)
FFF2h-FFF3h
5
ei3
External interrupt port B7..4
yes
yes1)
FFF0h-FFF1h
6
Not used
FFEEh-FFEFh
7
SPI
SPI peripheral interrupts
SPICSR
yes
yes1)
FFECh-FFEDh
8
TIMER A
TIMER A peripheral interrupts
TASR
no
FFEAh-FFEBh
9
TIMER B
TIMER B peripheral interrupts
TBSR
no
FFE8h-FFE9h
10
SCI
SCI Peripheral interrupts
SCISR
Lower
Priority
no
FFE6h-FFE7h
1
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