参数资料
型号: ST72F340K2T6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32
封装: 7 X 7 MM, LEAD FREE, LQFP-32
文件页数: 6/191页
文件大小: 3285K
代理商: ST72F340K2T6
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ST72340, ST72344, ST72345
103/191
SCI SERIAL COMMUNICATION INTERFACE (Cont’d)
11.5.4.3 Receiver
The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the SCICR1
register.
Character reception
During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, the
SCIDR register consists or a buffer (RDR) be-
tween the internal bus and the received shift regis-
ter (see Figure 1).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the SCIBRR
and the SCIERPR registers.
– Set the RE bit, this enables the receiver which
begins searching for a start bit.
When a character is received:
– The RDRF bit is set. It indicates that the content
of the shift register is transferred to the RDR.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
– The error flags can be set if a frame error, noise
or an overrun error has been detected during re-
ception.
Clearing the RDRF bit is performed by the following
software sequence done by:
1. An access to the SCISR register
2. A read to the SCIDR register.
The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.
Break Character
When a break character is received, the SCI han-
dles it as a framing error.
Idle Character
When an idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.
Overrun Error
An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can-
not be transferred from the shift register to the
RDR register until the RDRF bit is cleared.
When a overrun error occurs:
– The OR bit is set.
– The RDR content is not lost.
– The shift register is overwritten.
– An interrupt is generated if the RIE bit is set and
the I bit is cleared in the CCR register.
The OR bit is reset by an access to the SCISR reg-
ister followed by a SCIDR register read operation.
Noise Error
Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.
Normal data bits are considered valid if three con-
secutive samples (8th, 9th, 10th) have the same
bit value, otherwise the NF flag is set. In the case
of start bit detection, the NF flag is set on the basis
of an algorithm combining both valid edge detec-
tion and three samples (8th, 9th, 10th). Therefore,
to prevent the NF flag getting set during start bit re-
ception, there should be a valid edge detection as
well as three valid samples.
When noise is detected in a frame:
– The NF flag is set at the rising edge of the RDRF
bit.
– Data is transferred from the Shift register to the
SCIDR register.
– No interrupt is generated. However this bit rises
at the same time as the RDRF bit which itself
generates an interrupt.
The NF flag is reset by a SCISR register read op-
eration followed by a SCIDR register read opera-
tion.
During reception, if a false start bit is detected (e.g.
8th, 9th, 10th samples are 011,101,110), the
frame is discarded and the receiving sequence is
not started for this frame. There is no RDRF bit set
for this frame and the NF flag is set internally (not
accessible to the user). This NF flag is accessible
along with the RDRF bit when a next valid frame is
received.
Note: If the application Start Bit is not long enough
to match the above requirements, then the NF
Flag may get set due to the short Start Bit. In this
case, the NF flag may be ignored by the applica-
tion software when the first valid byte is received.
See also Section 0.1.4.10 .
Framing Error
A framing error is detected when:
– The stop bit is not recognized on reception at the
expected time, following either a de-synchroni-
zation or excessive noise.
– A break is received.
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相关代理商/技术参数
参数描述
ST72F340K4T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F340S2T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F340S4T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F344K2T6 功能描述:8位微控制器 -MCU 8 BITS MICROCONTR RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F344K4T6 功能描述:8位微控制器 -MCU 8-BIT MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT