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参数资料
| 型号： | ST72F60K2DIE1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, UUC |
| 文件页数： | 18/121页 |
| 文件大小： | 2515K |
| 代理商： | ST72F60K2DIE1 |
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ST7260
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16 KNOWN LIMITATIONS
16.1 PA2 LIMITATION WITH OCMP1 ENABLED
Description
This limitation affects only Rev B Flash devices
(with Internal Sales Type 72F60xxxxx$x7); it has
been corrected in Rev W Flash devices (with Inter-
nal Sales Type 72F60xxxxx$x9).
Note: Refer to Figure 68 on page 115
When Output Compare 1 function (OCMP1) on pin
PA6 is enabled by setting the OC1E bit in the
TCR2 register, pin PA2 is also affected.
In particular, the PA2 pin is forced to be floating
even if port configuration (PADDR+PADR) has set
it as output low. However, it can be still used as an
input.
16.2 UNEXPECTED RESET FETCH
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
16.3 SCI WRONG BREAK DURATION
Description
A single break character is sent by setting and re-
setting the SBK bit in the SCICR2 register. In
some cases, the break character may have a long-
er duration than expected:
- 20 bits instead of 10 bits if M=0
- 22 bits instead of 11 bits if M=1.
In the same way, as long as the SBK bit is set,
break characters are sent to the TDO pin. This
may lead to generate one break more than expect-
ed.
Occurrence
The occurrence of the problem is random and pro-
portional to the baudrate. With a transmit frequen-
cy
of
19200
baud
(fCPU=8MHz
and
SCI-
BRR=0xC9), the wrong break duration occurrence
is around 1%.
Workaround
If this wrong duration is not compliant with the
communication protocol in the application, soft-
ware can request that an Idle line be generated
before the break character. In this case, the break
duration is always correct assuming the applica-
tion is not doing anything between the idle and the
break. This can be ensured by temporarily disa-
bling interrupts.
The exact sequence is:
- Disable interrupts
- Reset and Set TE (IDLE request)
- Set and Reset SBK (Break Request)
- Re-enable interrupts
16.4 USB Behavior with LVD Disabled
On ROM devices, if the LVD is disabled, the USB
is disabled by hardware. So, the LVD is forced by
ST to 0 (LVD enabled). Refer to the ST7260 option
list for details.
相关PDF资料 |
PDF描述 |
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| ST72F60K2DIE6 | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, UUC |
| ST72F651AR6T1 | 8-BIT, FLASH, MICROCONTROLLER, PQFP64 |
| ST72P60E2M1 | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| ST7260E2M1/XXX | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24 |
| ST72T141K2M6XXX | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO34 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST72F60K2U1TR | 功能描述:8位微控制器 -MCU ST7262 Lo Spd USB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST72F621J4B1 | 功能描述:8位微控制器 -MCU Flash 16K USB/SPI/SC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST72F621J4D0 | 功能描述:8位微控制器 -MCU Flash 16K USB/SPI/SC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST72F621J4T1 | 功能描述:8位微控制器 -MCU ST7262 Lo Spd USB 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| ST72F621K4B1 | 功能描述:8位微控制器 -MCU Flash 16K USB/SPI/SC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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