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参数资料
型号： ST72P60E2M1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
封装： 0.300 INCH, LEAD FREE, PLASTIC, SOP-24
文件页数： 81/118页
文件大小： 2304K
代理商： ST72P60E2M1
ST7260
65/117
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
11.3.4.8 Clock Deviation Causes
The causes which contribute to the total deviation
are:
–DTRA: Deviation due to transmitter error (Local
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
–DQUANT: Error due to the baud rate quantisa-
tion of the receiver.
–DREC: Deviation of the local oscillator of the
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
–DTCL: Deviation due to the transmission line
(generally due to the transceivers)
All the deviations of the system should be added
and compared to the SCI clock tolerance:
DTRA + DQUANT + DREC + DTCL < 3.75%
11.3.4.9 Noise Error Causes
See also description of Noise error in Section
11.3.4.3.
Start bit
The noise flag (NF) is set during start bit reception
if one of the following conditions occurs:
1. A valid falling edge is not detected. A falling
edge is considered to be valid if the 3 consecu-
tive samples before the falling edge occurs are
detected as '1' and, after the falling edge
occurs, during the sampling of the 16 samples,
if one of the samples numbered 3, 5 or 7 is
detected as a “1”.
2. During sampling of the 16 samples, if one of the
samples numbered 8, 9 or 10 is detected as a
“1”.
Therefore, a valid Start Bit must satisfy both the
above conditions to prevent the Noise Flag getting
set.
Data Bits
The noise flag (NF) is set during normal data bit re-
ception if the following condition occurs:
– During the sampling of 16 samples, if all three
samples numbered 8, 9 and10 are not the same.
The majority of the 8th, 9th and 10th samples is
considered as the bit value.
Therefore, a valid Data Bit must have samples 8, 9
and 10 at the same value to prevent the Noise
Flag getting set.
Figure 37. Bit Sampling in Reception Mode
RDI LINE
Sample
clock
12345678910
11
12
13
14
15
16
sampled values
One bit time
6/16
7/16
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