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参数资料
型号： ST72P621L4M1
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO34
封装： PLASTIC, SO-34
文件页数： 51/136页
文件大小： 2475K
代理商： ST72P621L4M1
ST7262
21/136
6.2 RESET
The Reset procedure is used to provide an orderly
software start-up or to exit low power modes.
Three reset modes are provided: a low voltage re-
set, a watchdog reset and an external reset at the
RESET pin.
A reset causes the reset vector to be fetched from
addresses FFFEh and FFFFh in order to be loaded
into the PC and with program execution starting
from this point.
An internal circuitry provides a 514 CPU clock cy-
cle delay from the time that the oscillator becomes
active.
6.2.1 Low Voltage Reset
Low voltage reset circuitry generates a reset when
VDD is:
■ below VIT+ when VDD is rising,
■ below VIT- when VDD is falling.
During low voltage reset, the RESET pin is held low,
thus permitting the MCU to reset other devices.
Notes:
The Low Voltage Detector can be disabled by set-
ting the LVD bit of the Option byte.
It is recommended to make sure that the VDD supply
voltage rises monotonously when the device is ex-
iting from Reset, to ensure the application functions
properly.
6.2.2 Watchdog Reset
When a watchdog reset occurs, the RESET pin is
pulled low permitting the MCU to reset other devic-
es as when low voltage reset (Figure 15).
6.2.3 External Reset
The external reset is an active low input signal ap-
plied to the RESET pin of the MCU.
As shown in Figure 18, the RESET signal must
stay low for a minimum of one and a half CPU
clock cycles.
An internal Schmitt trigger at the RESET pin is pro-
vided to improve noise immunity.
Figure 15. Low Voltage Reset functional Diagram
Figure 16. Low Voltage Reset Signal Output
Note: Typical hysteresis (VIT+-VIT-) of 250 mV is
expected
Figure 17. Temporization Timing Diagram after an internal Reset
LOW VOLTAGE
VDD
FROM
WATCHDOG
RESET
INTERNAL
RESET
VDD
VIT+
VIT-
VDD
Addresses
$FFFE
Temporization
VIT+
(514 CPU clock cycles)
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