ST7L34, ST7L35, ST7L38, ST7L39
On-chip peripherals
Doc ID 11928 Rev 7
Setting the RWU bit by software puts the SCI in sleep mode:
All the reception status bits cannot be set.
All the receive interrupts are inhibited.
A muted receiver may be woken up in one of the following ways:
●
by idle line detection if the WAKE bit is reset,
●
by address mark detection if the WAKE bit is set.
Idle line detection
The receiver wakes up by idle line detection when the receive line has recognized an idle
line. Then the RWU bit is reset by hardware but the IDLE bit is not set.
This feature is useful in a multiprocessor system when the first characters of the message
determine the address and when each message ends by an idle line: As soon as the line
becomes idle, every receivers is waken up and analyse the first characters of the message
which indicates the addressed receiver. The receivers which are not addressed set RWU bit
to enter in mute mode. Consequently, they will not treat the next characters constituting the
next part of the message. At the end of the message, an idle line is sent by the transmitter:
this wakes up every receivers which are ready to analyse the addressing characters of the
new message.
In such a system, the inter-characters space must be smaller than the idle time.
Address mark detection
The receiver wakes up by address mark detection when it receives a ‘1’ as the most
significant bit of a word, thus indicating that the message is an address. The reception of
this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which
allows the receiver to receive this word normally and to use it as an address word.
This feature is useful in a multiprocessor system when the most significant bit of each
character (except for the break character) is reserved for address detection. As soon as the
receivers receive an address character (most significant bit = ’1’), the receivers are woken
up. The receivers which are not addressed set RWU bit to enter in mute mode.
Consequently, they will not treat the next characters constituting the next part of the
message.
Parity control
Hardware byte parity control (generation of parity bit in transmission and parity checking in
reception) can be enabled by setting the PCE bit in the SCICR1 register. Depending on the
character format defined by the M bit, the possible SCI character formats are as listed in
Note:
In case of wake-up by an address mark, the MSB bit of the data is taken into account and
not the parity bit
Table 61.
Character formats(1)
M bit
PCE bit
Character format
0
| SB | 8 bit data | STB |
1
| SB | 7-bit data | PB | STB |