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参数资料
| 型号： | ST7LNB1Y0M6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, EEPROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封装： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件页数： | 16/36页 |
| 文件大小： | 536K |
| 代理商： | ST7LNB1Y0M6 |
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ST7LNB1Y0
Electrical characteristics
5.3
Operating conditions
Table 21.
General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
VDD
Supply voltage
4.5
5.5
V
TA
Ambient temperature
40
+85
°C
Table 22.
Operating Conditions with Low Voltage Detector (LVD)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+(LVD)
Reset release threshold
(VDD rise)
4.00
4.25
4.50
V
VIT(LVD)
Reset generation threshold
(VDD fall)
3.80
4.10
4.30
Vhys
LVD voltage threshold
hysteresis
VIT+(LVD)VIT(LVD)
200
mV
VtPOR
VDD rise time rate
(1)
1.
Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on
and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the
MCU.
20
20000
s/V
tg(VDD)
Filtered glitch delay on VDD
Not detected by the LVD
150
ns
IDD(LVD) LVD/AVD current consumption
200
A
Table 23.
Operating conditions with the DiSEqC signalling
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fDiSEqC
DiSEqC tone frequency
17.6
22
26.4
kHz
VDiSEqC
DiSEqC tone voltage
100(1)
1.
The MCU is able to detect a DiSEqC signal with an amplitude from 100mV. However it is advised to ensure
a DiSEqC amplitude of at least 150 to 200mV to improve robustness against noise.
650
mVPP
VBackward
13/18 volt backward
compatibility voltage
threshold(2)
2.
In backwards compatible mode, bus DC voltage is compared with 15 V, if it exceeds this voltage then it is
considered as 18 V, otherwise it is considered as 13 V.
15
V
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