参数资料
型号: ST7PLITEUS2M6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8
封装: 0.150 INCH, LEAD FREE, PLASTIC, SOP-8
文件页数: 64/108页
文件大小: 1957K
代理商: ST7PLITEUS2M6
ST7LITEUSx
59/108
10-BIT A/D CONVERTER (ADC) (Cont’d)
10.3.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bits 4:3 = Reserved. Must be kept cleared.
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
Note: A write to the ADCCSR register (with ADON
set) aborts the current conversion, resets the EOC
bit and starts a new conversion.
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: 0000 0000 (00h)
Bits 7:0 = D[9:2] MSB of Analog Converted Value
DATA REGISTER LOW (ADCDRL)
Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = Reserved. Forced by hardware to 0.
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
Bit 2 = Reserved. Forced by hardware to 0.
Bits 1:0 = D[1:0] LSB of Analog Converted Value
70
EOC
SPEE
D
ADO
N
0
CH2
CH1
CH0
Channel Pin
CH2
CH1
CH0
AIN0
0
AIN1
0
1
AIN2
0
1
0
AIN3
0
1
AIN4
1
0
70
D9
D8
D7
D6
D5
D4
D3
D2
70
000
0
SLOW
0
D1
D0
fADC
SLOW SPEED
fCPU/2
0
fCPU
01
fCPU/4
1
x
1
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