参数资料
型号: ST7SCR1E4M1
厂商: 意法半导体
英文描述: 8-BIT LOW-POWER, FULL-SPEED USB MCU WITH 16K FLASH, 768 RAM, SMARTCARD I/F, TIMER
中文描述: 8位低功耗,全速USB微控制器与16K的闪存,768内存,智能卡的I /楼,计时器
文件页数: 64/102页
文件大小: 1413K
代理商: ST7SCR1E4M1
ST7SCR
64/102
SMARTCARD INTERFACE
(Cont’d)
SMARTCARD CONTACT CONTROL REGISTER
(CRDCCR)
Read/Write
Reset Value: 00xx xx00 (xxh)
Note:
To modify the content of this register, the LD
instruction must be used (do not use the BSET
and BRES instructions).
Bit 7 =
CLKSEL
Card clock selection.
This bit is set and cleared by software.
0: The signal on the CRDCLK pin is a copy of the
CRDCLK bit.
1: The signal on the CRDCLK pin is a 4MHz fre-
quency clock.
Note: T
o start the clock at a known level, the CRD-
CLK bit should be changed before the CLKSEL
bit.
Bit 6 = Reserved, must be kept cleared.
Bit 5 =
CRDC8
CRDC8 pin control.
Reading this bit returns the value present on the
CRDC8 pin. Writing this bit outputs the bit value on
the pin.
Bit 4 =
CRDC4
CRDC4 pin control
Reading this bit returns the value present on the
CRDC4 pin. Writing this bit outputs the bit value on
the pin.
Bit 3 =
CRDIO
CRDIO pin control
.
This bit is active only if the UART bit in the CRDCR
Register is reset. Reading this bit returns the value
present on the CRDIO pin.
If the UART bit
is reset:
– Writing “0” forces a low level on the CRDIO pin
– Writing “1” forces the CRDIO pin to open drain
Hi-Z.
Bit 2 =
CRDCLK
CRDCLK pin control
This bit is active only if the CLKSEL bit of the CRD-
CCR register is reset. Reading this bit returns the
value present in the register (not the CRDCLK pin
value).
When the CLKSEL bit is reset:
0: Level 0 to be applied on CRDCLK pin.
1: Level 1 to be applied on CRDCLK pin.
Note:
To ensure that the clock stops at a given
value, write the desired value in the CRDCLK bit
prior to changing the CLKSEL bit from 1 to 0.
Bit 1 =
CRDRST
CRDRST pin control.
Reading this bit returns the value present on the
CRDRST pin. Writing this bit outputs the bit value
on the pin.
Bit 0 =
CRDVCC
CRDVCC Pin Control.
This bit is set and cleared by software and forced
to 0 by hardware when no card is present
(CRDIRF bit=0).
0: No voltage to be applied on the CRDVCC pin.
1: The selected voltage must be applied on the
CRDVCC pin.
Figure 37. Smartcard I/O Pin Structure
7
0
CLK
SEL
-
CRD
C8
CRD
C4
CRD
IO
CRD
CLK
CRD
RST
CRD
VCC
I/O PIN
DATA BUS
CRDCCR
REGISTER
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