参数资料
型号: ST7SCR1R4T1
厂商: 意法半导体
英文描述: Enclosures; External Depth:18.50"; External Height:47.312"; External Width:22"; Panel Width:19.00"; Enclosure Color:Royal Blue; Enclosure Material:Steel; Panel Space:42.00" RoHS Compliant: Yes
中文描述: 8位低功耗,全速USB微控制器与16K的闪存,768内存,智能卡的I /楼,计时器
文件页数: 42/102页
文件大小: 1413K
代理商: ST7SCR1R4T1
ST7SCR
42/102
12.2 TIME BASE UNIT (TBU)
12.2.1 Introduction
The Timebase unit (TBU) can be used to generate
periodic interrupts.
12.2.2 Main Features
I
8-bit upcounter
I
Programmable prescaler
I
Period between interrupts: max. 8.1ms (at 8
MHz f
CPU
)
I
Maskable interrupt
12.2.3 Functional Description
The TBU operates as a free-running upcounter.
When the TCEN bit in the TBUCSR register is set
by software, counting starts at the current value of
the TBUCV register. The TBUCV register is incre-
mented at the clock rate output from the prescaler
selected by programming the PR[2:0] bits in the
TBUCSR register.
When the counter rolls over from FFh to 00h, the
OVF bit is set and an interrupt request is generat-
ed if ITE is set.
The user can write a value at any time in the
TBUCV register.
12.2.4 Programming Example
In this example, timer is required to generate an in-
terrupt after a delay of 1 ms.
Assuming that f
CPU
is 8 MHz and a prescaler divi-
sion factor of 256 will be programmed using the
PR[2:0] bits in the TBUCSR register, 1 ms = 32
TBU timer ticks.
In this case, the initial value to be loaded in the
TBUCV must be (256-32) = 224 (E0h).
ld A, E0h
ld TBUCV, A ; Initialize counter value
ld A 1Fh
;
ld TBUCSR, A ; Prescaler factor = 256,
; interrupt enable,
; TBU enable
Figure 26. TBU Block Diagram
TBU 8-BIT UPCOUNTER (TBUCV REGISTER)
INTERRUPT REQUEST
TBU PRESCALER
f
CPU
TBUCSR REGISTER
PR1
PR0
PR2
TCEN
ITE
OVF
MSB
LSB
0
0
1
TBU
0
1
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