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参数资料
| 型号： | ST92163V |
| 厂商： | 意法半导体 |
| 英文描述： | 8/16-BIT FULL SPEED USB MCU FOR COMPOSITE DEVICES WITH 16 ENDPOINTS, 20K ROM, 2K RAM, I2C, SCI, & MFT |
| 中文描述： | 16位产品全速USB微控制器16端点，20,000光盘和2K的RAM，I2C和脊髓损伤的复合设备， |
| 文件页数： | 170/224页 |
| 文件大小： | 1372K |
| 代理商： | ST92163V |
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ST92163 - SERIAL COMMUNICATIONS INTERFACE (SCI)
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
INTERRUPT/DMA PRIORITY REGISTER (IDPR)
R249 - Read/Write
Reset value: undefined
Bit 7 =
AMEN
: Address Mode Enable.
This bit, together with the AM bit (in the CHCR reg-
ister), decodes the desired addressing/9th data
bit/character match operation.
In Address modethe SCI monitors the input serial
data until its address is detected
Note:
Upon reception of address,the RXAP bit (in
the Interrupt Status Register) is set and an inter-
rupt cycle can begin. The address character will
not be transferred into the Receiver Buffer Regis-
ter but all data following the matched SCI address
and preceding thenext address word will be trans-
ferred to the Receiver Buffer Register and the
proper interrupts updated. If the address does not
match, all data following this unmatched address
will not be transferred to the Receiver Buffer Reg-
ister.
In any of the cases the RXAP bit must be reset by
software before the next word is transferred into
the Buffer Register.
When AMEN is reset and AM is set, a useful char-
acter searchfunction is performed. This allows the
SCI to generate an interrupt whenever a specific
character is encountered (e.g. Carriage Return).
Bit 6 =
SB
: Set Break
0: Stop the break transmission after minimum
break length.
1: Transmita break following thetransmission of all
data in the Transmitter Shift Register and the
Buffer Register.
Note:
Thebreak willbe a low level on the transmit-
ter data output for at least one complete word for-
mat. If software does not reset SB before the min-
imum break length has finished, the break condi-
tion will continue until software resets SB. TheSCI
terminates the break condition with a high level on
the transmitter data output for one transmission
clock period.
Bit 5 =
SA
: Set Address
If an address/9th data bit mode isselected, SA val-
ue will be loaded for transmission into the Shift
Register. This bit is cleared by hardware after its
load.
0: Indicate it is not an address word.
1: Indicate an address word.
Note:
Proper procedure would be, when the
Transmitter Buffer Register is empty, to load the
value of SA and then load the data into the Trans-
mitter Buffer Register.
Bit 4 =
RXD
: Receiver DMA Mask
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
receiver End of Block interrupt can occur.
0: Disable Receiver DMA request(the RXDP bit in
the S_ISR register can request an interrupt).
1: Enable Receiver DMA request (the RXDP bit in
the S_ISR register can requesta DMAtransfer).
Bit 3 =
TXD
: Transmitter DMA Mask
This bit is reset by hardware when the transaction
counter value decrements to zero. At that time a
transmitter End Of Block interrupt can occur.
0: Disable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request an interrupt).
1: Enable Transmitter DMA request (TXBEM or
TXSEM bits in S_ISR can request a DMA trans-
fer).
Bit 2:0=
PRL[2:0]
: SCI Interrupt/DMAPriority bits
The
priority
for
the
(PRL2,PRL1,PRL0). Priority level 0 is the highest,
while level 7 represents no priority.
When the user has defined a priority level for the
SCI, priorities within the SCI are hardware defined.
These SCI internal priorities are:
SCI
is
encoded
with
7
0
AMEN
SB
SA
RXD
TXD
PRL2
PRL1
PRL0
AMEN
0
0
AM
0
1
Address interrupt if 9th data bit = 1
Address interrupt if character match
Address interrupt if character match
and 9th data bit =1
Address interrupt if character match
with word immediately following Break
1
0
1
1
Receiver DMA request
Transmitter DMA request
Receiver interrupt
Transmitter interrupt
highest priority
lowest priority
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