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EXTENDED FUNCTION TIMER (EFT)
10.3 EXTENDED FUNCTION TIMER (EFT)
10.3.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (
input capture
) or generation of up to two out-
put waveforms (
output compare
and
PWM
).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the
INTCLK
prescaler.
10.3.2 Main Features
■
Programmable prescaler: INTCLK divided by 2,
4 or 8.
■
Overflow status flag and maskable interrupts
■
External clock input (must be at least 4 times
slower than the INTCLK
clock speed) with the
choice of active edge
■
Output compare functions with
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– Maskable interrupt generation
■
Input capture functions with
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– Maskable interrupt generation
■
Pulse width modulation mode (PWM)
■
One pulse mode
■
5 alternate functions on I/O ports
■
Global Timer interrupt (EFTI).
The Block Diagram is shown in
Figure 91
.
Table 35. EFT Pin Naming conventions
10.3.3 Functional Description
10.3.3.1 Counter
The principal block of the Programmable Timer is
a 16-bit free running counter and its associated
16-bit registers:
Counter Registers
– Counter High Register (CHR) is the most sig-
nificant byte (MSB).
– Counter Low Register (CLR) is the least sig-
nificant byte (LSB).
Alternate Counter Registers
– Alternate Counter High Register (ACHR) is the
m
ost significant
byte
(MSB).
– Alternate Counter Low Register (ACLR) is the
least significant byte (LSB).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (overflow
flag), (see note
page 168
).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
Table 36
. The
value in the counter register repeats every
131.072, 262.144 or 524.288 INTCLK cycles de-
pending on the CC[1:0] bits.
Function
Input Capture 1 - ICAP1
Input Capture 2 - ICAP2
Output Compare 1 - OCMP1 OCMPA0
Output Compare 2 - OCMP2 OCMPB0
EFT0
ICAPA0
ICAPB0
EFT1
ICAPA1
ICAPB1
OCMPA1
OCMPB1
9