December 2002
1/398
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 1.3
ST92F124/ST92F150/ST92F250
8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM,
E3 TM(EMULATED EEPROM), CAN 2.0B AND J1850 BLPD
PRELIMINARY DATA
s
Memories
– Internal Memory: Single Voltage FLASH up to 256
Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulat-
ed EEPROM)
– In-Application Programming (IAP)
– 224 general purpose registers (register file) availa-
ble as RAM, accumulators or index pointers
s
Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN, WFI,
SLOW, HALT and STOP modes
– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
– PLL Clock Generator (3-5 MHz crystal)
– Minimum instruction time: 83 ns (24 MHz int. clock)
s
80, 77 or 48 I/O pins (depending on device)
s
Interrupt Management
– 80, 77 or 48 I/O pins (depending on device)
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or addition-
al external interrupt with multi-level interrupt handler
– DMA controller for reduced processor overhead
s
Timers
– 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-
er (activated by software or by hardware)
– 16-bit Standard Timer that can be used to generate
a time base independent of PLL Clock Generator
– Two 16-bit independent Extended Function Timers
(EFTs) with Prescaler, 2 Input Captures and two
Output Compares (100-pin devices only)
– Two 16-bit Multifunction Timers, with Prescaler, 2 In-
put Captures and two Output Compares
s
Communication Interfaces
– Serial Peripheral Interface (SPI) with Selectable
Master/Slave mode
– One Multiprotocol Serial Communications Interface
with asynchronous and synchronous capabilities
– One asynchronous Serial Communications Interface
(on 100-pin versions only) with 13-bit LIN Synch
Break generation capability
– J1850 Byte Level Protocol Decoder (JBLPD)
(on F150J versions only)
– One or two full IC multiple Master/Slave Interfaces
supporting Access Bus
– One or two CAN 2.0B (150 version only) Active inter-
faces
s
10-bit Analog to Digital Converter allowing up to 16
input channels on 100-pin devices or 8 input channels
on 64-pin devices
s
Development Tools
– Free High performance Development environment
(IDE) based on Visual Debugger, Assembler, Linker,
and C-Compiler; Real Time Operating System (OS-
EK OS, CMX) and CAN drivers
– Hardware Emulator and Flash Programming Board
for development and ISP Flasher for production
DEVICE SUMMARY
1) see Section 12.3 on page 396 for important information
2) see Table 70 on page 393
PQFP100
14x20
TQFP64
14x14
TQFP100
14x14
Features
ST92F124R9
ST92F124V1
ST92F150C(R/V)1
ST92F150JDV1
ST92F250CV2
FLASH - bytes
64K
128K
256K
RAM - bytes
2K
4K
6K
8K
E3 TM - bytes
1K
Timers and Serial
Interface
2 MFT, STIM,
WD, SCI, SPI,
IC
2 MFT, 2 EFT,
STIM, WD,
2 SCI, SPI, IC
2 MFT, 0/2 EFT,
STIM, WD,
1/2 SCI, SPI, IC
2 MFT, 2 EFT,
STIM, WD,
2 SCI, SPI, IC
2 MFT, 2 EFT, STIM,
WD, 2 SCI,
SPI, 2 IC 1)
ADC
8 x 10 bits
16 x 10 bits
8/16 x 10 bits
16 x 10 bits
Network Interface
-
CAN
2 CAN, J1850
CAN, LIN Master
Temp. Range
-40°C to 85°C
-40°C to 105°C
-40°C to 105°C ,
-40°C to 125°C 2)
-40o C to 125o C
-40°C to 105°C ,
-40°C to 125°C 2)
Packages
TQFP64
PQFP100
P/TQFP100 and
TQFP64
P/TQFP100
9