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参数资料
| 型号： | ST92F150JV |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 1/8页 |
| 文件大小： | 65K |
| 代理商： | ST92F150JV |
June 2001
1/8
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 0.8
ST92F150
ST92F124
8/16-BIT FLASH MCU FAMILY
WITH RAM, EEPROM, CAN 2.0B AND J1850 BLPD
DATA BRIEFING
s
Memories
– Internal Memory: Single Voltage FLASH up to 128
Kbytes, RAM 2 to 6 Kbytes, EEPROM 512 to 1K
bytes
– 224 general purpose registers (register file) availa-
ble as RAM, accumulators or index pointers
s
Clock, Reset and Supply Management
– Register-oriented 8/16 bit CORE with RUN, WFI,
SLOW, HALT and STOP modes
– 0-24 MHz Operation (Int. Clock), 4.5-5.5 V range
– PLL Clock Generator (3-5 MHz crystal)
– Minimum instruction time: 83 ns (24 MHz int. clock)
s
Interrupt Management
– 77 (48 on TQFP64 version) I/O pins
– 4 external fast interrupts + 1 NMI
– Up to 16 pins programmable as wake-up or addition-
al external interrupt with multi-level interrupt handler
s
Timers
– 16-bit Timer with 8-bit Prescaler, and Watchdog Tim-
er (activated by software or by hardware)
– 16-bit Standard Timer that can be used to generate
a time base independent of PLL Clock Generator
– Two 16-bit independent Extended Function Timers
(EFTs) with Prescaler, 2 Input Captures and two
Output Compares (100-pin devices only)
– Two 16-bit Multifunction Timers, with Prescaler, 2 In-
put Captures and two Output Compares
s
Communication Interfaces
– Serial Peripheral Interface (SPI) with Selectable
Master/Slave mode
– One Multiprotocol Serial Communications Interface
with asynchronous and synchronous capabilities
– One asynchronous Serial Communications Interface
(on 100-pin versions only)
– J1850 Byte Level Protocol Decoder (JBLPD)
(on J versions only)
– Full I C multiple Master/Slave Interface supporting
Access Bus
– One or two CAN 2.0B (150 version only) Active inter-
faces with:
– Up to 1 MBit/s communication speed
– 3 Transmit Mailboxes with priority configuration
by software
– Enhanced Filtering mechanism
– 2 prioritized FIFO receive schemes
– Time-Triggered Communication support
s
DMA controller for reduced processor overhead
s
10-bit Analog to Digital Converter allowing up to
16 input channels on 100-pin devices or 8 input
channels on TQFP64
s
Instruction Set
– Rich Instruction Set with 14 Addressing Modes
– Division-by-zero trap generation
s
Development Tools
– Versatile Development Tools, including Assembler,
Linker, C-Compiler, Archiver, Source Level Debug-
ger, Hardware Emulators and Real Time Operating
System
DEVICE SUMMARY
PQFP100
TQFP64
TQFP100
Features
ST92F150JD
ST92F150JC
ST92F124
FLASH - bytes
128K
60/128K
RAM - bytes
6K
2/4K
EEPROM - bytes
1K
Timers
2 MFT, 2 EFT, STIM, WD
2 MFT, 0/2 EFT, STIM & WD
Serial Interface
2 SCI, SPI, I C
1/2 SCI, SPI, I C
ADC
16 x 10 bits
8/16 x 10 bits
Network Interface
2 CAN, J1850
CAN, J1850
-
Temp. Range
-40o Cto 125o C or -40oCto 85o C
Packages
P/TQF P100
P/TQ FP100 and TQFP64
9
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