参数资料
型号: ST93C06
厂商: 意法半导体
英文描述: 256 bit (16 x 16 or 32 x 8) Serial Microwire EEPROM(256位串行EEPROM)
中文描述: 256位(16 × 16或32 × 8)串行EEPROM的微型导线(256位串行EEPROM的)
文件页数: 9/15页
文件大小: 117K
代理商: ST93C06
EraseAll
The Erase All instruction (ERAL) erases the whole
memory (all memory bits are set to ’1’). A dummy
addressis input duringthe instructiontransfer and
the erase is made in the sameway as the ERASE
instruction. If the ST93C06 is still performing the
erasecycle,theBusysignal(Q=0) willbereturned
if S isdriven high,andthe ST93C06will ignoreany
data on the bus. When the erase cycle is com-
pleted, the Ready signal (Q = 1) will indicate (if S
is driven high)that theST93C06is readyto receive
a newinstruction.
Write All
For correct operation, an ERAL instruction should
be executed before the WRAL instruction: the
WRAL instructionDOESNOTperformanautomat-
ic erase before writing. The Write All instruction
(WRAL)writes theDataInputbyteorwordtoallthe
addresses of the memory. If the ST93C06 is still
performingthe write cycle, the Busy signal (Q = 0)
will bereturnedifSisdrivenhigh,andtheST93C06
will ignore any data on the bus. When the write
cycle is completed, the Ready signal (Q = 1) will
indicate (if S is driven high) that the ST93C06 is
ready to receive a new instruction.
READY/BUSY Status
During every programming cycle (after a WRITE,
ERASE, WRALor ERALinstruction) the Data Out-
put (Q) indicates the Ready/Busy status of the
memory when the Chip Select (S) is driven High.
Once the ST93C06 is Ready, the Ready/Busy
status is available on the Data Output (Q) until a
new start bit is decoded or the Chip Select (S) is
brought Low.
COMMONI/O OPERATION
The DataOutput (Q)andDataInput(D)signalscan
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memorywiththisconnection,mostly toprevent
a short circuit betweenthe lastentered address bit
(A0) and the first data bit output by Q. The reader
may also refer to the SGS-THOMSON application
note”MICROWIREEEPROMCommonI/OOpera-
tion”.
DIFFERENCES BETWEEN ST93C06 AND
ST93C06C
Each instruction of the ST93C06 requiresan Addi-
tional Dummy clock pulse after the rising edge of
the ChipSelect input(S)andbeforethe STARTbit,
see Figure 9. When replacing the ST93C06 with
the ST93C06C in an application, it must be
checkedthat this DummyClock cycle DOES NOT
HAPPENwhen D = 1: ifit is so,this clock pulsewill
latch an information which is decoded by the
ST93C06Casa STARTbit(see Figure 10)and the
following bits will bedecodedwitha shiftof one bit.
AI01334
1
C
S
D
0
Dummy Clock pulse
START Bit
Figure9. ST93C06Timing
9/15
ST93C06, ST93C06C
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