参数资料
型号: ST93C46CB6013TR
厂商: 意法半导体
英文描述: 1K 64 x 16 or 128 x 8 SERIAL MICROWIRE EEPROM
中文描述: 每1000 64 x 16或128 × 8 MICROWIRE的串行EEPROM的
文件页数: 9/13页
文件大小: 111K
代理商: ST93C46CB6013TR
READY/BUSY Status
During every programming cycle (after a WRITE,
ERASE, WRALor ERALinstruction) the Data Out-
put (Q) indicates the Ready/Busy status of the
memory whenthe ChipSelectis drivenHigh. Once
the ST93C46isReady,the Data Outputis setto ’1’
until a new start bit is decoded or the Chip Select
is brought Low.
COMMON I/O OPERATION
TheDataOutput(Q)andDataInput(D)signalscan
be connected together, through a current limiting
resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
the memorywith this connection,mostly to prevent
a shortcircuit betweenthe last enteredaddressbit
(A0) and the first data bit output by Q. The reader
should refer to the SGS-THOMSON application
note”MICROWIREEEPROMCommonI/OOpera-
tion”.
DIFFERENCES BETWEEN ST93C46A AND
ST93C46C
The ST93C46C is an enhanced version of the
ST93C46Aand offersthe followingextra features:
– EnhancedESD voltage
– Functionalsecurity filtering glitches on the
clock input(C).
Refer to Table 2 (Absolute Maximum Ratings) for
more about ESD limits. The following description
will detail the Clockpulsescounter (available only
on the ST93C46C).
In anormalenvironment,theST93C46is expected
to receivethe exactamountof dataon the D input,
that is the exact amount of clock pulses on the C
input.
In a noisy environment, the amount of pulses re-
ceived (on the clock input C) may be greater than
the clockpulsesdeliveredbytheMaster(Microcon-
troller) driving the ST93C46C. In such a case, a
part of the instruction is delayed by one bit (see
Figure 9), and it may inducean erroneouswrite of
data at a wrongaddress.
The ST93C46C has an on-board counter which
counts the clock pulses from the Start bit until the
falling edge of the Chip Select signal. For the
WRITE instructions, the number of clock pulses
incoming to the counter must be exactly 18 (with
the Organisation by 8) from the Start bit to the
fallingedge ofChipSelect signal(1 Startbit+2bits
of Op-code+ 7 bits of Address + 8 bits of Data =
18): if so, the ST93C46C executes the WRITE
instruction; if the number of clock pulses is not
equal to 18, the instruction will not be executed
(and data will not be corrupted).
In the same way, when the Organisationby 16 is
selected, the number of clock pulses incoming to
the countermust be exactly 25 (1 Startbit + 2 bits
of Op-code+ 6 bits of Address + 16 bits of Data =
25) from the Start bit to the falling edge of Chip
Select signal: if so, the ST93C46C executes the
WRITE instruction;if thenumber of clockpulses is
not equalto 25, theinstruction will not be executed
(and data will not be corrupted). The clock pulse
counter is active only on ERASE and WRITE in-
structions(WRITE, ERASE, ERAL, WRALL).
AI00880C
S
WRITE
ALL
DATA IN
D
Q
ADDR
OP
CODE
Dn
D0
BUSY
READY
CHECK
STATUS
1
0 0
0
1 Xn X0
Figure8. WRAL Sequence
Note:
1. Xn: n = 3 for x16 org. and 4 for x8 org.
9/13
ST93C46A/46C/46T, ST93C47C/47T
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