参数资料
型号: ST93C46CM1TR
厂商: 意法半导体
英文描述: 1K 64 x 16 or 128 x 8 SERIAL MICROWIRE EEPROM
中文描述: 每1000 64 x 16或128 × 8 MICROWIRE的串行EEPROM的
文件页数: 6/13页
文件大小: 111K
代理商: ST93C46CM1TR
MEMORY ORGANIZATION
The ST93C46 is organised as 128 bytes x8 bits or
64 words x 16 bits. If the ORG input is left uncon-
nected (or connectedto V
CC
) the x16 organization
is selected, when ORG is connected to Ground
(V
SS
) the x8 organization is selected. When the
ST93C46 is in standby mode, the ORG input
should be unconnectedor set to either V
SS
or V
CC
in order to get minimum power consumption.Any
voltagebetweenV
SS
andV
CC
appliedto ORGmay
increase the standby current value.
POWER-ON DATA PROTECTION
During power-up, A Power On Reset sequence is
run in order to reset all internal programming cir-
cuitry and the device is set in the Write Disable
mode. When V
CC
reaches its functionalvalue, the
deviceisproperlyreset (in the Write Disablemode)
and is ready to decode and execute an incoming
instruction.
INSTRUCTIONS
The ST93C46 has seven instructions, asshownin
Table 6. Eachinstruction is preceded by the rising
edgeof thesignalapplied ontheSinput(assuming
that theclock C is low), followed by a ’1’ read on D
input during the rising edge of the clock C. The
op-codes of the instructions are made up of the 2
followingbits.Someinstructionsuseonlythesefirst
two bits, others use also the first two bits of the
address to define the op-code. The op-code is
followed by an addressfor the byte/wordwhich is
made up of six bits for the x16 organization or
sevenbits for the x8 organization.
The ST93C46 is fabricated in CMOS technology
and is therefore able to run from zero Hz (static
inputsignals)up to themaximumratings (specified
in Table 5).
Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). Whena READinstruction
is received, the instruction and address are de-
codedand thedata from thememory is transferred
intoanoutputshiftregister.Adummy’0’bitisoutput
firstfollowedby the 8bitbyte orthe 16bitwordwith
the MSB first. Output data changes are triggered
by the Low to High transitionof theClock (C). The
ST93C46will automaticallyincrement the address
and will clock outthe next byte/word aslong as the
Chip Select input (S) is held High. In this case the
dummy ’0’ bit is NOT output between bytes/words
and a continuousstream of data can be read.
Erase/WriteEnable and Disable
The Erase/Write Enable instruction (EWEN)
authorizesthefollowingErase/Writeinstructionsto
be executed, the Erase/Write Disable instruction
(EWDS) freezes the execution of the following
Erase/Write instructions. When power is first ap-
plied to the ST93C46, Erase/Write is inhibited.
When the EWEN instruction is executed, Write
instructions remain enabled until an Erase/Write
Disableinstruction (EWDS)is executedorV
CC
falls
below the power-on reset threshold.To protect the
memory contents from accidental corruption, it is
advisabletoissuethe EWDSinstructionafterevery
write cycle.
The READ instruction is not affectedbythe EWEN
or EWDS instructions.
Instruction
Description
Op-Code
x8 Org
Address
(ORG = 0)
Data
x16 Org
Address
(ORG = 1)
Data
READ
Read Data from Memory
10
A6-A0
Q7-Q0
A5-A0
Q15-Q0
WRITE
Write Data to Memory
01
A6-A0
D7-D0
A5-A0
D15-D0
EWEN
Erase/Write Enable
00
11XXXXX
11XXXX
EWDS
Erase/Write Disable
00
00XXXXX
00XXXX
ERASE
Erase Byte or Word
11
A6-A0
A5-A0
ERAL
Erase All Memory
00
10XXXXX
10XXXX
WRAL
Write All Memorywith same Data
00
01XXXXX
D7-D0
01XXXX
D15-D0
Note:
X = don’t carebit.
Table 6. InstructionSet
6/13
ST93C46A/46C/46T, ST93C47C/47T
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