STD90/MDL90
x
Samsung ASIC
Contents
Analog Interface
VDDA/VDDD .................................................................................................................................4-89
VSSD/VSSA/VBBA .......................................................................................................................4-89
PIA_BB/PIAR10_BB/PIAR50_BB/PIC_BB/PICC_BB...................................................................4-89
POA_BB/POAR50_BB/POT2_BB/POT4_BB/POT12_BB.............................................................4-89
5
Compiled Macrocells
Overview to Compiled Macrocells.................................................................................................5-1
Characteristics for Timing and Power............................................................................................5-2
Built-In Self Test for Compiled Memory.........................................................................................5-3
Selection Guide for Compiled Memory..........................................................................................5-4
SPSRAM_HD................................................................................................................................5-5
SPSRAMBW_HD..........................................................................................................................5-15
DPSRAM_HD................................................................................................................................5-25
SPARAM_HD ................................................................................................................................5-35
DROM_HD....................................................................................................................................5-45
MROM_HD....................................................................................................................................5-53
Compiled Datapath Macrocells ....................................................................................................5-59
Datapath Module Design Flow......................................................................................................5-59
Selection Guide for Compiled Datapath Macrocells......................................................................5-60
ADDER..........................................................................................................................................5-61
ALU ...............................................................................................................................................5-66
BS .................................................................................................................................................5-70
CSADDER.....................................................................................................................................5-75
BMPY............................................................................................................................................5-79
REGF ............................................................................................................................................5-86
6
PLL
AL2007LX .....................................................................................................................................6-1
AL2007LA .....................................................................................................................................6-9