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参数资料
| 型号： | STEL-1375A+80 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP35 |
| 封装： | 2.500 X 1.300 INCH, 0.350 INCH HEIGHT, DIP-35 |
| 文件页数： | 8/13页 |
| 文件大小： | 202K |
| 代理商： | STEL-1375A+80 |
STEL-1375A+80
4
INPUT SIGNALS
RESET
The RESET input is asynchronous and active low.
When RESET goes low, all registers are cleared within
30 nsecs. The signal on the OUT pin will then be
invalid for 7 clock cycles, and thereafter will remain at
the value corresponding to zero phase until a new
frequency or phase is loaded into the
-Phase Register
or Phase Register with a FRLD or PHLD command
after the RESET returns high.
CLOCK
All synchronous functions performed within the NCO
are referenced to the rising edge of the CLOCK input.
The CLOCK signal should be nominally a square
wave or sine wave at a maximum frequency of 80
MHz.
A non-repetitive CLOCK waveform is
permissible as long as the minimum duration positive
or negative pulses on the waveform are always greater
than 5 nanoseconds.
CSEL
The CSEL (Chip Select) input is active low and can be
used to control the writing of data into the chip. When
this input is high all data writing via the DATA7-0 bus
is inhibited.
DATA7 through DATA0
The eight bit DATA7-0 bus is used to program the 32 bit
-Phaseregistersandthe12-bitPhaseregister. DATA
0
is the least significant bit of the bus.
ADDR3 through ADDR0
The four address lines ADDR3-0 control the use of the
DATA7-0 bus for writing frequency data to the -Phase
Buffer Registers and phase data to the Phase
Modulation Registers, as shown in the tables:
ADDR3 ADDR2
Register Selected
00
-Phase Register 'A'
01
-Phase Register 'B'
1
X
Phase Modulation Register
ADDR3 ADDR1 ADDR0
Register Field
0
Bits 7–0 (LSB)
0
1
Bits 15–8
0
1
0
Bits 23–16
0
1
Bits 31–24
1
0
Bits 3–0(LSB)*
1
0
1
Bits 11-4*
* Notes: The Phase Modulation Register is a 12-bit
register. When the least significant byte of this register
CIRCUIT DESCRIPTION
The frequency of the NCO is determined by the number
stored in the
-Phase register which is programmed
from the interface bus. The number stored in the
-Phase register is added to the current contents of the
accumulator every clock cycle to generate a
monotonically increasing phase angle.
The NCO
generates digitized sine and cosine functions by
addressing a sine/cosine lookup table with the phase
accumulator. Phase modulation data is added to the
accumulator output before the lookup table.
The NCO is controlled from a microprocessor based
interface. Bytes of data can be written into the frequency
and phase control registers from the data bus. For
high-speed phase modulation it is also possible to load
the phase modulation data as a parallel 12-bit word.
Please refer to the STEL-1175 data sheet for information
on programming the NCO.
The NCO output is loaded synchronously into a high-
speed 10-bit DAC which incorporates CMOS-ECL level
translators and a fixed voltage reference circuit..
FUNCTION BLOCK
DESCRIPTION
NCO BLOCK
The NCO block is the core of the STEL-1375A+80 DDS.
It consists of a front-end which may be programmed
from the control inputs. The NCO is described fully in
the STEL-1175 data sheet. Please refer to this data sheet
for more detailed information.
CLOCK GENERATION BLOCK
The clock generation block generates the different
clocks required for the NCO and DAC blocks from the
incoming sinusoidal clock signal.
DAC BLOCK
The DAC block consists of the AD9721 digital to analog
converter and the necessary supporting circuitry. The
DAC incorporates CMOS to ECL translation circuits
and a reference generator. The reference level, which
determines the output signal level, is not adjustable.
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