- 您现在的位置：买卖IC网 > PDF目录98147 > STEL-1377Q (INTEL CORP) SPECIALTY MICROPROCESSOR CIRCUIT, DIP63 PDF资料下载
参数资料
| 型号： | STEL-1377Q |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP63 |
| 封装： | 3.750 X 1.600 INCH, 0.40 INCH HEIGHT, DIP-63 |
| 文件页数： | 8/13页 |
| 文件大小： | 231K |
| 代理商： | STEL-1377Q |
STEL-1377Q/S
4
CIRCUIT DESCRIPTION
The frequency of the NCO is determined by the
number stored in the
-Phase register which is
programmed from the interface bus. The number
stored in the
-Phase register is added to the current
contents of the accumulator every clock cycle to
generate a monotonically increasing phase angle. By
modulating this number the frequency of the NCO can
be modulated. The NCO generates digitized sine and
cosine functions by addressing sine and cosine lookup
tables with the phase accumulator. Phase modulation
data is added to the accumulator output before the
lookup tables. Please refer to the STEL-1177 data sheet
for information on programming the NCO.
The NCO output is passed through CMOS to ECL level
translators and loaded synchronously into two high-
speed 10-bit DACs. The full-scale outputs of the DACs
is determined by the voltage on the VREF input, and
this can be used to amplitude modulate the output
signals.
FUNCTION BLOCK DESCRIPTION
NCO BLOCK
The NCO block is the core of the STEL-1377 DDS. It
consists of a front-end which may be programmed
from the control inputs. The NCO is described fully in
the STEL-1177 data sheet. Please refer to this data sheet
for more detailed information.
LEVEL TRANSLATOR BLOCK
The outputs of the NCO block are CMOS level digital
signals.
These are translated to ECL levels for
optimum operation of the DAC.
CLOCK GENERATION BLOCK
The clock generation block generates the different
clocks required for the NCO and DAC blocks from the
incoming ECL or sinusoidal clock signal.
DAC BLOCK
The DAC block consists of the Sony CX20201A-1
digital to analog converters and the necessary
supporting circuitry.
INPUT SIGNALS
RESET
The RESET input is asynchronous and active low, and
clears all the registers in the device. When RESET goes
low, all registers are cleared within 20 nsecs, and
normal operation will resume after this signal returns
high. The outputs will go to the zero level during the
reset, and thereafter will remain at the value
corresponding to zero phase until new frequency or
modulation (either frequency or phase) data is loaded
with the FRLD, FMLD, or PHLD inputs after the
RESET
returns high.
CLOCK
All synchronous functions performed within the NCO
are referenced to the rising edge of the CLOCK input.
The CLOCK signal should be a square wave or sine
wave at a maximum frequency of 60 MHz. A non-
repetitive CLOCK waveform is permissible as long as
the minimum duration positive or negative pulse on
the waveform is always greater than 5 nanoseconds.
CSEL
The Chip Select input is used to control the writing of
data into the chip. It is active low. When this input is
high all data writing via the DATA7-0 bus is inhibited.
DATA7 through DATA0
The 8-bit DATA7-0 bus is used to program the two 32-
bit
-Phase Registers and the two 12-bit Phase
Modulation Registers. DATA0 is the least significant
bit of the bus. The data programmed into the
-Phase
registers in this way determines the carrier frequency
of the NCO.
ADDR3 through ADDR0
The four address lines ADDR3-0 control the use of the
DATA7-0 bus for writing frequency data to the -Phase
Buffer Registers, and phase data to the Phase Buffer
Registers, as shown in the table:
ADDR3 ADDR1 ADDR0 Register Field
00
0
-Phase Bits 0 (LSB)–7
00
1
-Phase Bits 8–15
01
0
-Phase Bits 16–23
01
1
-Phase Bits 24–31
1
0
Sine Bits 0(LSB)–3*
1
0
1
Sine Bits 4-11*
1
0
Cosine Bits 0(LSB)–3*
1
Cosine Bits 4-11*
ADDR3 ADDR2
Register Selected
00
-Phase Buffer Register 'A'
01
-Phase Buffer Register 'B'
1
X
Phase Buffer Registers
Note: The Phase Buffer Registers are 12-bit registers.
When the least significant bytes of these registers are
selected (ADDR3-0 =1XX0), DATA7-4 is written into
相关PDF资料 |
PDF描述 |
|---|---|
| STK1390-5S25I | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| STK1390-5S30I | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| STK1390-5S35 | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| STK1390-5W30I | 0 TIMER(S), REAL TIME CLOCK, PDIP32 |
| STK1390-5W35 | 0 TIMER(S), REAL TIME CLOCK, PDIP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| STEL-1377S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC |
| STEL-1378A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FREQUENCY SYNTHESIZER|HYBRID|DIP|64PIN|PLASTIC |
| STEL-2000A+20/CR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:RF MODULATOR/DEMODULATOR|CMOS|QFP|100PIN|PLASTIC |
| STEL-2000A+45/CR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:RF MODULATOR/DEMODULATOR|CMOS|QFP|100PIN|PLASTIC |
| STEL2020 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Convolutional-FEC-Viterbi Error Circuit - Burst and continuous modes |
发布紧急采购，3分钟左右您将得到回复。