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参数资料
| 型号： | STEL-1377S |
| 英文描述： | FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC |
| 中文描述： | 频率合成器|双酯| 64管脚|塑料 |
| 文件页数： | 8/19页 |
| 文件大小： | 284K |
| 代理商： | STEL-1377S |
STEL-2060C
8
must follow the rising edge of SYMCKIN by a minimum of
8 nsec. at this instant, otherwise the handover will not occur
correctly. This occurs once every 4 cycles of DCLKIN at rate
7
/
8
, every 2 cycles at rate
3
/
4
and every 3 cycles at rate
2
/
3
, the
number of cycles of SYMCKIN depending on whether the
parallel or sequential input mode is used, as well as the code
rate. Two examples of clock phasing for rate
3
/
4
parallel
operation are shown below.
Here, the timing is such that the falling edges of DCLKIN
only coincide with falling edges of SYMCKIN, never with
rising edges. In this case the timing violation never occurs at
any speed, since the non-coincident falling edges of DCLKIN
will trail the rising edges of SYMCKIN by approximately 8
nsec. at a speed of 45 Mbps. Again, the same caveat regarding
jitter must be observed. However, the symbol signal setup
and hold requirements, shown in page 11 of the data sheet
make it necessary for SYMCKIN to have a minimum low
time of 12 nsec. to satisfy these requirements, so that it is not
possible for this signal to be a square wave above 40 MHz for
this reason. Since the method for eliminating the clock
timing violation presented here relies on the use of square
waves (50% mark-space ratio), it cannot be used above 40
MHz because of the setup and hold time requirements.
Again, a similar condition exists for rate
7
/
8
operation, as
shown below.
SYMCKIN
DCLKIN
Good
Bad
In the first example the falling edges of DCLKIN never
coincide with the rising edges of SYMCKIN. Thus the timing
violation will never occur provided that the delay from the
non-coincident rising edges of SYMCKIN to the following
falling edge of DCLKIN (shown by the arrows) exceeds 8
nsec. In the second case the falling edge of DCLKIN coincides
with the rising edge of SYMCKIN once every two cycles of
DCLKIN, resulting in a 50% probability that this may be the
point at which the handover occurs, creating the problem
discussed above.
There are several ways to satisfy the timing requirement,
depending on the code rate. One effective way which works
at all rates is to generate SYMCKIN from DCLKIN by
puncturing the clock to reduce its frequency while keeping
all the edges synchronized; this will require the use of a small
FIFO to buffer the input symbols to cope with the punctured
clock. The rate
3
/
4
timing is shown below as an example.
SYMCKIN
DCLKIN
For rate
3
/
4
operation it is possible to generate the two clocks
with a mutual phase relationship that can exclude the timing
violation, as was shown in the first figure. As previously
stated, provided the two clocks can be generated as shown in
the first example, where only the
rising
edges of DCLKIN
coincide with the edges of SYMCKIN, the timing violation
will never occur provided that the delay from the non-
coincident rising edges of SYMCKIN to the following falling
edge of DCLKIN (shown by the arrows) exceeds 8 nsec. In
the example shown this will be true at data rates up to 30
Mbps. Care must be taken to ensure that jitter between the
clocks is kept low enough to avoid the timing violation
condition. A similar condition exists for rate
2
/
3
operation,
as shown below.
SYMCKIN
DCLKIN
SYMCKIN
DCLKIN
However, in this case the timing violation will begin to occur
at speeds over 15 Mbps, so that this method of solving the
timing problem is less useful for rate
7
/
8
operation.
Note that for sequential mode operation (PARL = 0) the
frequency of the SYMCKIN signal will be doubled in every
case. This presents a problem with the synchronized clock
method presented here since it will not be possible to generate
the necessary waveforms with the correct mutual phasing
guaranteed because of the phase ambiguity of the SYMCKIN
signal itself relative to the internal handover process. In this
case it will be necessary to use either the punctured clock
approach or the synchronized reset approach.
The third method, which, while having the disadvantage
that it is susceptible to loss of sync from disturbances, is
easier to implement than clock puncturing and provides a lot
more margin than simple clock phase synchronization. It
consists of a synchronized reset generator used in conjunction
with clock phase synchronization. This is shown below for
rate
7
/
8
.
RESET
SYMCKIN
DCLKIN
15 nsec. min.
This ensures that the STEL-2060CC starts up during the
optimum phase of the SYMCKIN/DCLKIN repetition cycle,
i.e., the phase with the maximum separation between the
rising edge of SYMCKIN and the next falling edge of DCLKIN;
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| STEL-1378A | FREQUENCY SYNTHESIZER|HYBRID|DIP|64PIN|PLASTIC |
| STEPHY1 | Semiconductor Fuse; Current Rating:35A; Voltage Rating:250V; Fuse Type:Fast Acting; Fuse Terminals:Blade; Diameter:20.6mm; Length:81mm; Series:L25S; Voltage Rating:250V |
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| STF203-15.TC | Analog Miscellaneous |
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