参数资料
型号: STK1743-D45
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, DIP28
封装: 0.600 INCH, MODULE, DIP-28
文件页数: 12/12页
文件大小: 314K
代理商: STK1743-D45
STK1743
January 2003
9
Document Control # ML0011 rev 0.0
accessed during this period. It is important that
READ
cycles and not WRITE cycles be used in the
sequence, although it is not necessary that G be
low for the sequence to be valid. After the t
STORE
cycle time has been fulfilled, the SRAM will again be
activated for READ and WRITE operation.
SOFTWARE NONVOLATILE RECALL
A software RECALL cycle is initiated with a
sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the
RECALL
cycle, the following sequence of READ
operations must be performed:
1. Read address
0000 (hex)
Valid READ
2. Read address
1555 (hex)
Valid READ
3. Read address
0AAA (hex)
Valid READ
4. Read address
1FFF (hex)
Valid READ
5. Read address
10F0 (hex)
Valid READ
6. Read address
0F0E (hex)
Initiate RECALL cycle
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
After the t
RECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL
operation in no way alters the data in the
Nonvolatile Elements cells. The nonvolatile data
can be recalled an unlimited number of times. Note
that the RTC registers are not affected by nonvola-
tile operations.
AutoStoreTM OPERATION
The STK1743 uses capacitance built into the mod-
ule to perform an automatic STORE on power down.
In order to prevent unnecessary STORE operations,
automatic STOREs will be ignored unless at least
one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software-
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place.
POWER-UP RECALL
During power up, or after any low-power condition
(V
CC < VRESET), an internal RECALL request will be
latched. When V
CC once again exceeds VSWITCH, a
RECALL
cycle will automatically be initiated and will
take t
RESTORE to complete.
If the STK1743 is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor
should be connected either between W and system
V
CC or between E and system VCC.
HARDWARE PROTECT
The STK1743 offers hardware protection against
inadvertent STORE and SRAM WRITE operation dur-
ing low-voltage conditions. When V
CC < VSWITCH, all
software STORE operations and SRAM writes are
inhibited.
LOW AVERAGE ACTIVE POWER
The STK1743 draws significantly less current when
it is cycled at times longer than 50ns. Figure 2
shows the relationship between I
CC and READ cycle
time. Worst-case current consumption is shown for
both CMOS and TTL input levels (commercial tem-
perature range, V
CC = 5.5V, 100% duty cycle on chip
enable). Figure 3 shows the same relationship for
WRITE
cycles. If the chip enable duty cycle is less
than 100%, only standby current is drawn when the
chip is disabled. The overall average current drawn
by the STK1743 depends on the following items:
1) CMOS vs. TTL input levels; 2) the duty cycle of
chip enable; 3) the overall cycle rate for accesses;
4) the ratio of READs to WRITEs; 5) the operating
temperature; 6) the V
CC level; and 7) I/O loading.
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