- 您现在的位置：买卖IC网 > PDF目录98148 > STK17TA8-R25I REAL TIME CLOCK, PDSO48 PDF资料下载
参数资料
| 型号： | STK17TA8-R25I |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO48 |
| 封装： | 0.300 INCH, 0.025 INCH PITCH, PLASTIC, SSOP-48 |
| 文件页数： | 9/25页 |
| 文件大小： | 285K |
| 代理商： | STK17TA8-R25I |
STK17TA8
April 2005
Document Control #ML0025 rev 1.1
17
continuously. The MSB of each alarm register is a
Match bit. Selecting none of the Match bits (all 1’s)
indicates that no match is required. The alarm occurs
every second. Setting the match select bit for seconds
to “0” causes the logic to match the seconds alarm
value to the current time of day. Since a match will
occur for only one value per minute, the alarm occurs
once per minute. Likewise, setting the seconds and
minutes Match bits causes an exact match of these
values. Thus, an alarm will occur once per hour.
Setting seconds, minutes and hours causes a match
once per day. Lastly, selecting all match values
causes an exact time and date match. Selecting other
bit combinations will not produce meaningful results;
however the alarm circuit should follow the functions
described.
There are two ways a user can detect an alarm event,
by reading the AF flag or monitoring the INT pin. The
AF flag in the flags register at 0x1FFF0 will indicate
that a date/time match has occurred. The AF bit will
be set to 1 when a match occurs. Reading the
Flags/Control register clears the alarm flag bit (and all
others). A hardware interrupt pin may also be used to
detect an alarm event.
WATCHDOG TIMER
The watchdog timer is a free running down counter
that uses the 32 Hz clock (31.25 ms) derived from the
crystal oscillator. The oscillator must be running for
the watchdog to function. It begins counting down
from the value loaded in the Watchdog Timer register.
The counter consists of a loadable register and a free
running counter. On power up, the watchdog time-out
value in register 0x1FFF7 is loaded into the counter
load register. Counting begins on power up and
restarts from the loadable value any time the
Watchdog Strobe (WDS) bit is set to 1. The counter is
compared to the terminal value of 0. If the counter
reaches this value, it causes an internal flag and an
optional interrupt output. The user can prevent the
time-out interrupt by setting WDS bit to 1 prior to the
counter reaching 0. This causes the counter to be
reloaded with the watchdog time-out value and to be
restarted. As long as the user sets the WDS bit prior
to the counter reaching the terminal value, the inter-
rupt and flag never occurs.
New time-out values can be written by setting the
watchdog write bit to 0. When the WDW is 0 (from the
previous operation), new writes to the watchdog time-
out value bits D5-D0 allow the time-out value to be
modified. When WDW is a 1, then writes to bits D5-D0
will be ignored. The WDW function allows a user to
set the WDS bit without concern that the watchdog
timer value will be modified. A logical diagram of the
watchdog timer is shown below. Note that setting the
watchdog time-out value to 0 would be otherwise
meaningless and therefore disables the watchdog
function.
The output of the watchdog timer is a flag bit WDF
that is set if the watchdog is allowed to time-out. The
flag is set upon a watchdog time-out and cleared
when the Flags/Control register is read by the user.
The user can also enable an optional interrupt source
to drive the INT pin if the watchdog time-out occurs.
POWER MONITOR
The STK17TA8 provides a power management
scheme with power-fail interrupt capability. It also
controls the internal switch to backup power for the
clock and protects the memory from low-VCC access.
The power monitor is based on an internal band-gap
reference circuit that compares the VCC voltage to
various thresholds.
As described in the AutoStore section previously,
when Vswitch is reached as VCC decays from power
loss, a data store operation is initiated from SRAM to
the nonvolatile elements, securing the last SRAM
data state. Power is also switched from VCC to the
backup supply (battery or capacitor) to operate the
RTC oscillator.
When operating from the backup source no data may
be read or written and the clock functions are not
available to the user. The clock continues to operate
in the background. Updated clock data is available to
Oscillator
Clock
Divider
Counter
Load
Register
Zero
Compare
Watchdog
Register
WDS
WDF
WDW
32 Hz
1 Hz
D Q
Q
write to
Watchdog
Register
32.768KH2
Figure 7. Watchdog Timer Block Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| STK17TA8-R35 | REAL TIME CLOCK, PDSO48 |
| STK17TA8-W25 | REAL TIME CLOCK, PDIP40 |
| STK17TA8-R45 | REAL TIME CLOCK, PDSO48 |
| STK17TA8-R25 | REAL TIME CLOCK, PDSO48 |
| STK17TA8RF25I | REAL TIME CLOCK, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| STK17TA8-RF25 | 功能描述:NVRAM 128Kbx8+RTC 2.7-3.6V RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| STK17TA8-RF25I | 功能描述:NVRAM 128Kbx8+RTC 2.7-3.6V RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| STK17TA8-RF25IL | 制造商:Cypress Semiconductor 功能描述: |
| STK17TA8-RF25ITR | 功能描述:NVRAM 128Kbx8+RTC 2.7-3.6V RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| STK17TA8-RF25TR | 功能描述:NVRAM 128Kbx8+RTC 2.7-3.6V RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
发布紧急采购，3分钟左右您将得到回复。