参数资料
型号: STM32F101C6T6XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 36 MHz, RISC MICROCONTROLLER, QCC48
封装: 7 X 7 MM, ROHS COMPLIANT, LQFP-48
文件页数: 57/77页
文件大小: 1203K
代理商: STM32F101C6T6XXX
Electrical characteristics
STM32F101x4, STM32F101x6
Doc ID 15058 Rev 4
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 40 are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 8.
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 40.
SPI characteristics(1)
1.
Remapped SPI characteristics to be determined.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
0
18
MHz
Slave mode
0
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
tsu(NSS)
(2)
2.
Based on characterization, not tested in production.
NSS setup time
Slave mode
4 tPCLK
th(NSS)
NSS hold time
Slave mode
73
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
tsu(MI)
Data input setup time
Master mode
SPI
1
tsu(SI)
Data input setup time
Slave mode
1
th(MI)
Data input hold time
Master mode
SPI
1
th(SI)
Data input hold time
Slave mode
3
ta(SO)
(2)(3)
3.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access time
Slave mode, fPCLK = 36 MHz,
presc = 4
055
Slave mode, fPCLK = 24 MHz
0
4 tPCLK
tdis(SO)
(2)(4)
4.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable time Slave mode
10
tv(SO)
Data output valid time
Slave mode (after enable edge)
25
tv(MO)
Data output valid time
Master mode (after enable
edge)
3
th(SO)
Data output hold time
Slave mode (after enable edge)
25
th(MO)
Master mode (after enable
edge)
4
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