参数资料
型号: STM32F103RCT6TR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP64
封装: 10 X 10 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-64
文件页数: 103/122页
文件大小: 1599K
代理商: STM32F103RCT6TR
STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Doc ID 14611 Rev 6
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
5.3.13
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL
compliant.
Table 44.
Electrical sensitivities
Symbol
Parameter
Conditions
Class
LU
Static latch-up class
TA +105 °C conforming to JESD78A
II level A
Table 45.
I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL
Input low level voltage
TTL ports
–0.5
0.8
V
VIH
Standard IO input high level voltage
2
VDD+0.5
IO FT(1) input high level voltage
2
5.5V
VIL
Input low level voltage
CMOS ports
–0.5
0.35 VDD
V
VIH
Input high level voltage
0.65 VDD
VDD+0.5
Vhys
Standard IO Schmitt trigger voltage
hysteresis(2)
200
mV
IO FT Schmitt trigger voltage
hysteresis(2)
5% VDD
(3)
mV
Ilkg
Input leakage current (4)
VSS VIN VDD
Standard I/Os
1
A
VIN= 5 V, I/O FT
3
RPU
Weak pull-up equivalent resistor(5)
VIN VSS
30
40
50
k
RPD
Weak pull-down equivalent resistor(5)
VIN VDD
30
40
50
k
CIO
I/O pin capacitance
5
pF
1.
FT = Five-volt tolerant.
2.
Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
3.
With a minimum of 100 mV.
4.
Leakage could be higher than max. if negative current is injected on adjacent pins.
5.
Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order)
.
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