STM32F103RCY6XXX PDF资料下载(25/122 页)32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA64

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参数资料

型号：	STM32F103RCY6XXX
厂商：	STMICROELECTRONICS
元件分类：	微控制器/微处理器
英文描述：	32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA64
封装：	4.466 X 4.395 MM, 0.50 MM PITCH, ROHS COMPLIANT, WLCSP-64
文件页数：	25/122页
文件大小：	1599K
代理商：	STM32F103RCY6XXX

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Revision history

STM32F103xC, STM32F103xD, STM32F103xE

Doc ID 14611 Rev 6

30-Mar-2009

5

I/O information clarified on page 1. Figure 4: STM32F103xC,

STM32F103xD and STM32F103xE performance line BGA100 ballout

corrected.

I/O information clarified on page 1.

In Table 5: High-density STM32F103xx pin definitions:

– I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15

updated

– PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default

column to Remap column

PG14 pin description modified in Table 6: FSMC pin definition.

Figure 9: Memory map on page 38 modified.

Note modified in Table 14: Maximum current consumption in Run mode,

code with data processing running from Flash and Table 16: Maximum

current consumption in Sleep mode, code running from Flash or RAM.

Figure 16, Figure 17 and Figure 18 show typical curves (titles

changed).

Table 21: High-speed external user clock characteristics and Table 22:

Low-speed external user clock characteristics modified. ACCHSI max

values modified in Table 25: HSI oscillator characteristics.

FSMC configuration modified for Asynchronous waveforms and timings.

Notes modified below Figure 23: Asynchronous non-multiplexed

SRAM/PSRAM/NOR read waveforms and Figure 24: Asynchronous

non-multiplexed SRAM/PSRAM/NOR write waveforms.

tw(NADV) values modified in Table 31: Asynchronous non-multiplexed

SRAM/PSRAM/NOR read timings and Table 34: Asynchronous

multiplexed PSRAM/NOR write timings. th(Data_NWE) modified in

Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write

In Table 36: Synchronous multiplexed PSRAM write timings and

Table 38: Synchronous non-multiplexed PSRAM write timings:

–tv(Data-CLK) renamed as td(CLKL-Data)

–td(CLKL-Data) min value removed and max value added

–th(CLKL-DV) / th(CLKL-ADV) removed

Figure 27: Synchronous multiplexed NOR/PSRAM read timings,

Figure 28: Synchronous multiplexed PSRAM write timings and

Figure 30: Synchronous non-multiplexed PSRAM write timings

modified.

Figure 47: I2S slave timing diagram (Philips protocol)(1) and Figure 48:

I2S master timing diagram (Philips protocol)(1) modified.

WLCSP64 package added (see Figure 8: STM32F103xC,

STM32F103xD and STM32F103xE performance line WLCSP64

ballout, ball side, Table 5: High-density STM32F103xx pin definitions,

Figure 60: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-

level chip-scale package outline and Table 66: WLCSP, 64-ball 4.466 ×

4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical

Small text changes.

Table 72.

Document revision history

Date

Revision

Changes

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相关代理商/技术参数	参数描述
STM32F103RCY7TR	制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103RCY7XXX	制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103RD	制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103RDH6TR	制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103RDH6XXX	制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces

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