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参数资料
型号： STM32F103RDT6TR
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP64
封装： 10 X 10 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-64
文件页数： 25/122页
文件大小： 1599K
代理商： STM32F103RDT6TR
Revision history
STM32F103xC, STM32F103xD, STM32F103xE
120/122
Doc ID 14611 Rev 6
30-Mar-2009
5
I/O information clarified on page 1. Figure 4: STM32F103xC,
STM32F103xD and STM32F103xE performance line BGA100 ballout
corrected.
I/O information clarified on page 1.
In Table 5: High-density STM32F103xx pin definitions:
– I/O level of pins PF11, PF12, PF13, PF14, PF15, G0, G1 and G15
updated
– PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default
column to Remap column
PG14 pin description modified in Table 6: FSMC pin definition.
Figure 9: Memory map on page 38 modified.
Note modified in Table 14: Maximum current consumption in Run mode,
code with data processing running from Flash and Table 16: Maximum
current consumption in Sleep mode, code running from Flash or RAM.
Figure 16, Figure 17 and Figure 18 show typical curves (titles
changed).
Table 21: High-speed external user clock characteristics and Table 22:
Low-speed external user clock characteristics modified. ACCHSI max
values modified in Table 25: HSI oscillator characteristics.
FSMC configuration modified for Asynchronous waveforms and timings.
Notes modified below Figure 23: Asynchronous non-multiplexed
SRAM/PSRAM/NOR read waveforms and Figure 24: Asynchronous
non-multiplexed SRAM/PSRAM/NOR write waveforms.
tw(NADV) values modified in Table 31: Asynchronous non-multiplexed
SRAM/PSRAM/NOR read timings and Table 34: Asynchronous
multiplexed PSRAM/NOR write timings. th(Data_NWE) modified in
Table 32: Asynchronous non-multiplexed SRAM/PSRAM/NOR write
timings
In Table 36: Synchronous multiplexed PSRAM write timings and
Table 38: Synchronous non-multiplexed PSRAM write timings:
–tv(Data-CLK) renamed as td(CLKL-Data)
–td(CLKL-Data) min value removed and max value added
–th(CLKL-DV) / th(CLKL-ADV) removed
Figure 27: Synchronous multiplexed NOR/PSRAM read timings,
Figure 28: Synchronous multiplexed PSRAM write timings and
Figure 30: Synchronous non-multiplexed PSRAM write timings
modified.
Figure 47: I2S slave timing diagram (Philips protocol)(1) and Figure 48:
I2S master timing diagram (Philips protocol)(1) modified.
WLCSP64 package added (see Figure 8: STM32F103xC,
STM32F103xD and STM32F103xE performance line WLCSP64
ballout, ball side, Table 5: High-density STM32F103xx pin definitions,
Figure 60: WLCSP, 64-ball 4.466 × 4.395 mm, 0.500 mm pitch, wafer-
level chip-scale package outline and Table 66: WLCSP, 64-ball 4.466 ×
4.395 mm, 0.500 mm pitch, wafer-level chip-scale package mechanical
data).
Small text changes.
Table 72.
Document revision history
Date
Revision
Changes
相关PDF资料
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STM32F103RCT6TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP64
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相关代理商/技术参数
参数描述
STM32F103RDT6XXX 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103RDT7TR 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103RDT7XXX 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
STM32F103RDY6 制造商:STMicroelectronics 功能描述:16/32-BITS MICROS - Tape and Reel
STM32F103RDY6TR 功能描述:ARM微控制器 - MCU 32-Bit Cortex 64Kb Performance Line RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 处理器系列:STM32F373xx 数据总线宽度:32 bit 最大时钟频率:72 MHz 程序存储器大小:256 KB 数据 RAM 大小:32 KB 片上 ADC:Yes 工作电源电压:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作温度范围:- 40 C to + 85 C 封装 / 箱体:LQFP-48 安装风格:SMD/SMT
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