参数资料
型号: STM32F103T6U7TR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, QCC36
封装: 6 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, VFQFPN-36
文件页数: 60/80页
文件大小: 1067K
代理商: STM32F103T6U7TR
STM32F103x4, STM32F103x6
Electrical characteristics
Doc ID 15060 Rev 3
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 45 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 9.
Note:
It is recommended to perform a calibration after each power-up.
Table 45.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
2.4
3.6
V
VREF+
Positive reference voltage
2.4
VDDA
V
IVREF
Current on the VREF input pin
160(1)
220(1)
A
fADC
ADC clock frequency
0.6
14
MHz
fS
(2)
Sampling rate
0.05
1
MHz
fTRIG
External trigger frequency
fADC = 14 MHz
823
kHz
17
1/fADC
VAIN
(3)
Conversion voltage range
0 (VSSA tied to
ground)
VREF+
V
RAIN
External input impedance
Table 46 for details
50
k
RADC
Sampling switch resistance
1
k
CADC
Internal sample and hold
capacitor
8pF
Calibration time
fADC = 14 MHz
5.9
s
83
1/fADC
Injection trigger conversion
latency
fADC = 14 MHz
0.214
s
3(4)
1/fADC
tlatr
Regular trigger conversion
latency
fADC = 14 MHz
0.143
s
1/fADC
tS
Sampling time
fADC = 14 MHz
0.107
17.1
s
1.5
239.5
1/fADC
tSTAB
Power-up time
0
1
s
tCONV
Total conversion time
(including sampling time)
fADC = 14 MHz
1
18
s
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1.
Based on characterization, not tested in production.
2.
Guaranteed by design, not tested in production.
3.
In devices delivered in VFQFPN and LQFP packages, VREF+ is internally connected to VDDA and VREF- is internally
connected to VSSA. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF- pin (VREF- is internally
connected to VSSA), see Table 5 and Figure 4.
4.
For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 45.
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