参数资料
型号: STM32F103VBT6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP100
封装: 14 X 14 MM, 0.50 MM PITCH, LQFP-100
文件页数: 60/79页
文件大小: 1124K
代理商: STM32F103VBT6
STM32F103xx
Electrical characteristics
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 7.
Note:
It is recommended to perform a calibration after each power-up.
Table 43.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
ADC power supply
2.4
3.6
V
VREF+
Positive reference voltage
2.4
VDDA
V
fADC
ADC clock frequency
0.6
14
MHz
fS
Sampling rate
TBD
0.05
1
MHz
fTRIG
External trigger frequency
fADC = 14 MHz
823
kHz
17
1/fADC
VAIN
Conversion voltage range(1)
0 (VSSA or VREF-
tied to ground)
VDDA or
VREF+
V
RAIN
External input impedance
k
Ilkg
Negative input leakage current
on analog pins
VIN < VSS, | IIN | < 400 A
on adjacent analog pin
56
A
RADC
Sampling switch resistance
1
k
CADC
Internal sample and hold
capacitor
5pF
tCAL
Calibration time
fADC = 14MHz
5.9
s
83
1/fADC
tlat
Injection trigger conversion
latency
fADC = 14 MHz
0.228
s
3(2)
fADC
tlatr
Regular trigger conversion
latency
fADC = 14 MHz
0.228
s
fADC
tS
Sampling time
fADC = 14 MHz
0.107
17.1
s
1.5
239.5
1/fADC
tSTAB
Power-up time
0
1
s
tCONV
Total conversion time
(including sampling time)
fADC = 14 MHz
118
s
14 to 252 (tS for sampling +12.5 for
successive approximation)
1/fADC
1.
VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 3: Pin descriptions for further details.
2.
For internal triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 43.
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