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参数资料
型号： STM32F103VDH7XXX
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA100
封装： 10 X 10 MM, 0.50 MM PITCH, ROHS COMPLIANT, LFBGA-100
文件页数： 5/122页
文件大小： 1599K
代理商： STM32F103VDH7XXX
Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
102/122
Doc ID 14611 Rev 6
5.3.19
DAC electrical specifications
Table 62.
DAC characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Comments
VDDA
Analog supply voltage
2.4
3.6
V
VREF+
Reference supply voltage
2.4
3.6
V
VREF+ must always be below VDDA
VSSA
Ground
0
V
RLOAD
(1)
Resistive load with buffer
ON
5k
RO
(1)
Impedance output with
buffer OFF
15
k
When the buffer is OFF, the Minimum
resistive load between DAC_OUT
and VSS to have a 1% accuracy is
1.5 M
CLOAD
(1)
Capacitive load
50
pF
Maximum capacitive load at
DAC_OUT pin (when the buffer is
ON).
DAC_OUT
min(1)
Lower DAC_OUT voltage
with buffer ON
0.2
V
It gives the maximum output
excursion of the DAC
it corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VREF+ = 3.6 V
and (1x55) and (0xEAB) at VREF+ =
2.4 V
DAC_OUT
max(1)
Higher DAC_OUT voltage
with buffer ON
VDDA – 0.2 V
IDDVREF+
DAC DC current
consumption in quiescent
mode (Standby mode)
220
A
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
IDDA
DAC DC current
consumption in quiescent
mode (Standby mode)
380
A
With no load, middle code (0x800) on
the inputs
480
A
With no load, worst code (0xF1C) at
VREF+ = 3.6 V in terms of DC
consumption on the inputs
DNL(2)
Differential non linearity
Difference between two
consecutive code-1LSB)
±0.5
LSB
Given for the DAC in 10-bit
configuration
±2
LSB
Given for the DAC in 12-bit
configuration
INL(2)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
±1
LSB
Given for the DAC in 10-bit
configuration
±4
LSB
Given for the DAC in 12-bit
configuration
相关PDF资料
PDF描述
STM32F103RCY6XXX 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA64
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相关代理商/技术参数
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