参数资料
型号: STM32F103ZDT7XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, 0.50 MM PITCH, ROHS COMPLIANT, LQFP-144
文件页数: 115/122页
文件大小: 1599K
代理商: STM32F103ZDT7XXX
Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Doc ID 14611 Rev 6
Table 53.
I2S characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
DuCy(SCK)
I2S slave input clock duty
cycle
Slave mode
30
70
%
fCK
1/tc(CK)
I2S clock frequency
Master mode (data: 16 bits,
Audio frequency = 48 kHz)
1.522
1.525
MHz
Slave mode
0
6.5
tr(CK)
tf(CK)
I2S clock rise and fall time
Capacitive load CL =50 pF
8
ns
tv(WS)
(1)
WS valid time
Master mode
3
th(WS)
WS hold time
Master mode
I2S2
2
I2S3
0
tsu(WS)
WS setup time
Slave mode
4
th(WS)
WS hold time
Slave mode
0
tw(CKH)
CK high and low time
Master fPCLK= 16 MHz, audio
frequency = 48 kHz
312.5
tw(CKL)
345
tsu(SD_MR)
Data input setup time
Master receiver
I2S2
2
I2S3
6.5
tsu(SD_SR)
Data input setup time
Slave receiver
1.5
th(SD_MR)
(1)(2)
Data input hold time
Master receiver
0
th(SD_SR)
Slave receiver
0.5
tv(SD_ST)
Data output valid time
Slave transmitter (after enable
edge)
18
th(SD_ST)
Data output hold time
Slave transmitter (after enable
edge)
11
tv(SD_MT)
Data output valid time
Master transmitter (after enable
edge)
3
th(SD_MT)
Data output hold time
Master transmitter (after enable
edge)
0
1.
Based on design simulation and/or characterization results, not tested in production.
2.
Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
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