参数资料
型号: STM32F107VBH6XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
封装: ROHS COMPLIANT, LFBGA-100
文件页数: 9/90页
文件大小: 998K
代理商: STM32F107VBH6XXX
STM32F105xx, STM32F107xx
Description
2.4.7
IC bus
Up to two IC bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A
hardware CRC generation/verification is embedded.
They can be served by DMA and they support SMBus 2.0/PMBus.
2.4.8
Universal synchronous/asynchronous receiver transmitters (USARTs)
The STM32F105xx and STM32F107xx connectivity line embeds three universal
synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3) and
two universal asynchronous receiver transmitters (UART4 and UART5).
These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and
have LIN Master/Slave capability.
The USART1 interface is able to communicate at speeds of up to 4.5 Mbit/s. The other
available interfaces communicate at up to 2.25 Mbit/s.
USART1, USART2 and USART3 also provide hardware management of the CTS and RTS
signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All
interfaces can be served by the DMA controller except for UART5.
2.4.9
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
All SPIs can be served by the DMA controller.
2.4.10
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available, that can be
operated in master or slave mode. These interfaces can be configured to operate with 16/32
bit resolution, as input or output channels. Audio sampling frequencies from 8 kHz up to
96 kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency with less than 0.5% accuracy error owing to the advanced clock
Please refer to the “Audio frequency precision” tables provided in the “Serial peripheral
interface (SPI)” section of the STM32F10xxx reference manual.
2.4.11
Ethernet MAC interface with dedicated DMA and IEEE 1588 support
Peripheral not available on STM32F105xx devices.
The STM32F107xx devices provide an IEEE-802.3-2002-compliant media access controller
(MAC) for ethernet LAN communications through an industry-standard media-independent
interface (MII) or a reduced media-independent interface (RMII). The STM32F107xx
requires an external physical interface device (PHY) to connect to the physical LAN bus
相关PDF资料
PDF描述
STM32F105VBH7XXX 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F105VCH6TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F105VCH7XXX 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F107VBH6TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F107VBH7TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
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