参数资料
型号: STM32F205RBY7TR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PBGA66
封装: 0.40 MM PITCH, ROHS COMPLIANT, WLCSP-66
文件页数: 5/163页
文件大小: 2275K
代理商: STM32F205RBY7TR
Electrical characteristics
STM32F205xx, STM32F207xx
102/163
Doc ID 15818 Rev 7
Table 50.
I2S characteristics(1)
1.
TBD stands for “to be defined”.
Symbol
Parameter
Conditions
Min
Max
Unit
fCK
1/tc(CK)
I2S clock frequency
Master
TBD
MHz
Slave
0
TBD
tr(CK)
tf(CK)
I2S clock rise and fall time
capacitive load
CL = 50 pF
-
TBD
ns
tv(WS)
(2)
2.
Based on design simulation and/or characterization results, not tested in production.
WS valid time
Master
TBD
-
th(WS)
WS hold time
Master
TBD
-
tsu(WS)
WS setup time
Slave
TBD
-
th(WS)
WS hold time
Slave
TBD
-
tw(CKH)
tw(CKL)
CK high and low time
Master fPCLK= TBD,
presc = TBD
TBD
-
tsu(SD_MR)
tsu(SD_SR)
Data input setup time
Master receiver
Slave receiver
TBD
-
th(SD_MR)
th(SD_SR)
3.
Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.
Data input hold time
Master receiver
Slave receiver
TBD
-
th(SD_MR)
th(SD_SR)
Data input hold time
Master fPCLK = TBD
Slave fPCLK = TBD
TBD
-
tv(SD_ST)
Data output valid time
Slave transmitter
(after enable edge)
-
TBD
fPCLK = TBD
-
TBD
th(SD_ST)
Data output hold time
Slave transmitter
(after enable edge)
TBD
-
tv(SD_MT)
Data output valid time
Master transmitter
(after enable edge)
-
TBD
fPCLK = TBD
TBD
th(SD_MT)
Data output hold time
Master transmitter
(after enable edge)
TBD
-
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