参数资料
型号: STM32F205RET7XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PQFP64
封装: 10 X 10 MM, ROHS COMPLIANT, LQFP-64
文件页数: 107/163页
文件大小: 2275K
代理商: STM32F205RET7XXX
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Table 6.
Alternate function mapping
Port
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF014
AF15
SYS
TIM1/2
TIM3/4/5
TIM8/9/10/11
I2C1/I2C2/I2C3
SPI1/SPI2/I2S2
SPI3/I2S3
USART1/2/3
UART4/5/
USART6
CAN1/CAN2/
TIM12/13/14
OTG_FS/ OTG_HS
ETH
FSMC/SDIO/
OTG_FS
DCMI
PA0-WKUP
TIM2_CH1
TIM2_ETR
TIM 5_CH1
TIM8_ETR
USART2_CTS
UART4_TX
ETH_MII_CRS
EVENTOUT
PA1
TIM2_CH2
TIM5_CH2
USART2_RTS
UART4_RX
ETH_MII _RX_CLK
ETH_RMII _REF_CLK
EVENTOUT
PA2
TIM2_CH3
TIM5_CH3
TIM9_CH1
USART2_TX
ETH_MDIO
EVENTOUT
PA3
TIM2_CH4
TIM5_CH4
TIM9_CH2
USART2_RX
OTG_HS_ULPI_D0
ETH _MII_COL
EVENTOUT
PA4
SPI1_NSS
SPI3_NSS
I2S3_WS
USART2_CK
OTG_HS_SOF
DCMI_HSYNC
EVENTOUT
PA5
TIM2_CH1
TIM2_ETR
TIM8_CH1N
SPI1_SCK
OTG_HS_ULPI_CK
EVENTOUT
PA6
TIM1_BKIN
TIM3_CH1
TIM8_BKIN
SPI1_MISO
TIM13_CH1
DCMI_PIXCK
EVENTOUT
PA7
TIM1_CH1N
TIM3_CH2
TIM8_CH1N
SPI1_MOSI
TIM14_CH1
ETH_MII _RX_DV
ETH_RMII _CRS_DV
EVENTOUT
PA8
MCO1
TIM1_CH1
I2C3_SCL
USART1_CK
OTG_FS_SOF
EVENTOUT
PA9
TIM1_CH2
I2C3_SMBA
USART1_TX
DCMI_D0
EVENTOUT
PA10
TIM1_CH3
USART1_RX
OTG_FS_ID
DCMI_D1
EVENTOUT
PA11
TIM1_CH4
USART1_CTS
CAN1_RX
OTG_FS_DM
EVENTOUT
PA12
TIM1_ETR
USART1_RTS
CAN1_TX
OTG_FS_DP
EVENTOUT
PA13
JTMS-SWDIO
EVENTOUT
PA14
JTCK-SWCLK
EVENTOUT
PA15
JTDI
TIM 2_CH1
TIM 2_ETR
SPI1_NSS
SPI3_NSS
I2S3_WS
EVENTOUT
PB0
TIM1_CH2N
TIM3_CH3
TIM8_CH2N
OTG_HS_ULPI_D1
ETH _MII_RXD2
EVENTOUT
PB1
TIM1_CH3N
TIM3_CH4
TIM8_CH3N
OTG_HS_ULPI_D2
ETH _MII_RXD3
OTG_HS_INTN
EVENTOUT
PB2
EVENTOUT
PB3
JTDO/
TRACESWO
TIM2_CH2
SPI1_SCK
SPI3_SCK
I2S3_SCK
EVENTOUT
PB4
JTRST
TIM3_CH1
SPI1_MISO
SPI3_MISO
EVENTOUT
PB5
TIM3_CH2
I2C1_SMBA
SPI1_MOSI
SPI3_MOSI
I2S3_SD
CAN2_RX
OTG_HS_ULPI_D7
ETH _PPS_OUT
DCMI_D10
EVENTOUT
PB6
TIM4_CH1
I2C1_SCL
USART1_TX
CAN2_TX
OTG_FS_INTN
DCMI_D5
EVENTOUT
PB7
TIM4_CH2
I2C1_SDA
USART1_RX
FSMC_NL
DCMI_VSYNC
EVENTOUT
PB8
TIM4_CH3
TIM10_CH1
I2C1_SCL
CAN1_RX
OTG_FS_SCL
ETH _MII_TXD3
SDIO_D4
DCMI_D6
EVENTOUT
PB9
TIM4_CH4
TIM11_CH1
I2C1_SDA
SPI2_NSS
I2S2_WS
CAN1_TX
OTG_FS_SDA
SDIO_D5
DCMI_D7
EVENTOUT
PB10
TIM2_CH3
I2C2_SCL
SPI2_SCK
I2S2_SCK
USART3_TX
OTG_HS_ULPI_D3
ETH_ MII_RX_ER
OTG_HS_SCL
EVENTOUT
PB11
TIM2_CH4
I2C2_SDA
USART3_RX
OTG_HS_ULPI_D4
ETH _MII_TX_EN
ETH _RMII_TX_EN
OTG_HS_SDA
EVENTOUT
PB12
TIM1_BKIN
I2C2_SMBA
SPI2_NSS
I2S2_WS
USART3_CK
CAN2_RX
OTG_HS_ULPI_D5
ETH _MII_TXD0
ETH _RMII_TXD0
OTG_HS_ID
EVENTOUT
PB13
TIM1_CH1N
SPI2_SCK
I2S2_SCK
USART3_CTS
CAN2_TX
OTG_HS_ULPI_D6
ETH _MII_TXD1
ETH _RMII_TXD1
EVENTOUT
PB14
TIM1_CH2N
TIM8_CH2N
SPI2_MISO
USART3_RTS
TIM12_CH1
OTG_HS_DM
EVENTOUT
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