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参数资料
型号： STM32F205VCT7XXX
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PQFP100
封装： 14 X 14 MM, ROHS COMPLIANT, LQFP-100
文件页数： 19/163页
文件大小： 2275K
代理商： STM32F205VCT7XXX
STM32F205xx, STM32F207xx
Electrical characteristics
Doc ID 15818 Rev 7
115/163
INL(3)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
--
±1
LSB
Given for the DAC in 10-bit
configuration.
--
±4
LSB
Given for the DAC in 12-bit
configuration.
Offset(3)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VREF+/2)
--
±10
mV
Given for the DAC in 12-bit
configuration
--
±3
LSB
Given for the DAC in 10-bit at
VREF+ = 3.6 V
--
±12
LSB
Given for the DAC in 12-bit at
VREF+ = 3.6 V
Gain
error(3)
Gain error
-
±0.5
%
Given for the DAC in 12-bit
configuration
tSETTLING
(3)
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
highest input codes when
DAC_OUT reaches final
value ±4LSB
-3
6
s
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
THD(3)
Total Harmonic Distortion
Buffer ON
--
-
dB
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
Update
rate(2)
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
--
1
MS/s
CLOAD ≤ 50 pF,
RLOAD ≥ 5 kΩ
tWAKEUP
(3)
Wakeup time from off state
(Setting the ENx bit in the
DAC Control register)
-6.5
10
s
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
input code between lowest and
highest possible ones.
PSRR+ (2)
Power supply rejection ratio
(to VDDA) (static DC
measurement)
-
–67
–40
dB
No RLOAD, CLOAD = 50 pF
1.
If IRROFF is set to VDD, this value can be lowered to 1.65 V when the device operates in a reduced temperature range.
2.
Guaranteed by design, not tested in production.
3.
Guaranteed by characterization, not tested in production.
Table 63.
DAC characteristics (continued)
Symbol
Parameter
Min
Typ
Max
Unit
Comments
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