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参数资料
型号： STM32F205ZFT7XXX
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PQFP144
封装： 20 X 20 MM, ROHS COMPLIANT, LQFP-144
文件页数： 163/163页
文件大小： 2275K
代理商： STM32F205ZFT7XXX
STM32F205xx, STM32F207xx
Electrical characteristics
Doc ID 15818 Rev 7
99/163
I2S - SPI interface characteristics
Unless otherwise specified, the parameters given in Table 49 for SPI or in Table 50 for I2S
are derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 10.
Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 49.
SPI characteristics(1)(2)
1.
Remapped SPI1 characteristics to be determined.
2.
TBD stands for “to be defined”.
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
-
30
MHz
Slave mode
-
30
tr(SCL)
tf(SCL)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
-
8
ns
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
30
70
%
tsu(NSS)
(3)
3.
Based on characterization, not tested in production.
NSS setup time
Slave mode
4 tPCLK
-
ns
th(NSS)
(3)
NSS hold time
Slave mode
2 tPCLK
-
tw(SCLH)
(3)
tw(SCLL)
(3)
SCK high and low time
Master mode, fPCLK = 30 MHz,
presc = 4
TBD
tsu(MI)
(3)
tsu(SI)
(3)
Data input setup time
Master mode
5
-
Slave mode
5
-
th(MI)
(3)
th(SI)
(3)
Data input hold time
Master mode
5
-
Slave mode
4
-
ta(SO)
(3)(4)
4.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access
time
Slave mode, fPCLK = 20 MHz
0
3 tPCLK
tdis(SO)
(3)(5)
5.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable
time
Slave mode
2
10
tv(SO)
(3)(1)
Data output valid time
Slave mode (after enable edge)
-
25
tv(MO)
(3)(1)
Data output valid time
Master mode (after enable edge)
-
5
th(SO)
(3)
Data output hold time
Slave mode (after enable edge)
15
-
th(MO)
(3)
Master mode (after enable edge)
2
-
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