参数资料
型号: STM8AF52A8TCU
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP48
封装: 7 X 7 MM, ROHS COMPLIANT, LQFP-48
文件页数: 32/120页
文件大小: 2236K
代理商: STM8AF52A8TCU
STM8AF52/62xx, STM8AF51/61xx
Product overview
Doc ID 14395 Rev 7
5.5.3
Internal 128 kHz RC oscillator
The frequency of this clock is 128 kHz and it is independent from the main clock. It drives
the independent watchdog or the AWU wakeup timer.
In systems which do not need independent clock sources for the watchdog counters, the
128 kHz signal can be used as the system clock. This configuration has to be enabled by
setting an option byte (OPT3/OPT3N, bit LSI_EN).
5.5.4
Internal high-speed crystal oscillator
The internal high-speed crystal oscillator can be selected to deliver the main clock in normal
run mode. It operates with quartz crystals and ceramic resonators.
Frequency range: 1 MHz to 24 MHz
Crystal oscillation mode: preferred fundamental
I/Os: standard I/O pins multiplexed with OSCIN, OSCOUT
5.5.5
External clock input
An external clock signal can be applied to the OSCIN input pin of the crystal oscillator. The
frequency range is 0 to 24 MHz.
5.5.6
Clock security system (CSS)
The clock security system protects against a system stall in case of an external crystal clock
failure.
In case of a clock failure an interrupt is generated and the high-speed internal clock (HSI) is
automatically selected with a frequency of 2 MHz (16 MHz/8).
5.6
Low-power operating modes
The product features various low-power modes:
Slow mode: prescaled CPU clock, selected peripherals at full clock speed
Active halt mode: CPU and peripheral clocks are stopped, the device cyclically goes
back to run mode, controlled by the AWU timer. Wakeup through external events is
possible.
Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
Wakeup is triggered by an external interrupt.
In all modes the CPU and peripherals remain permanently powered on, the system clock is
applied only to selected modules. The RAM content is preserved and the brown-out reset
circuit remains activated.
5.7
Timers
5.7.1
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications. The watchdog timer activity is controlled by the application program or
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