参数资料
型号: STM8L101F2U3ATR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, QCC20
封装: 3 X 3 MM, 0.60 MM HEIGHT, ROHS COMPLIANT, UFQFPN-20
文件页数: 55/79页
文件大小: 1942K
代理商: STM8L101F2U3ATR
STM8L101xx
Electrical parameters
Doc ID 15275 Rev 8
Inter IC control interface (I2C)
Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.
The STM8L I2C interface meets the requirements of the Standard I2C communication
protocol described in the following table with the restriction mentioned below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Note:
For speeds around 200 kHz, achieved speed can have
± 5% tolerance
For other speed ranges, achieved speed can have
± 2% tolerance
The above variations depend on the accuracy of the external components used.
Table 32.
I2C characteristics
Symbol
Parameter
Standard mode
I2C
Fast mode I2C(1)
1.
fSCK must be at least 8 MHz to achieve max fast I
2C speed (400 kHz).
Unit
Min(2)
2.
Data based on standard I2C protocol requirement, not tested in production.
Max (2)
Min (2)
Max (2)
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
μs
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
ns
th(SDA)
SDA data hold time
0 (3)
3.
The maximum hold time of the START condition has only to be met if the interface does not stretch the low
period of SCL signal.
-0 (4)
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL).
900 (3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
START condition hold time
4.0
-
0.6
-
μs
tsu(STA)
Repeated START condition setup
time
4.7
-
0.6
-
tsu(STO)
STOP condition setup time
4.0
-
0.6
-
μs
tw(STO:STA)
STOP to START condition time (bus
free)
4.7
-
1.3
-
μs
Cb
Capacitive load for each bus line
-
400
-
400
pF
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